wave.fit.eqn

数字示波器的FPGA实现 VHDL编写 Quartus7.1测试通过

N1_TEMP[7] = DFFEA(N1L71, !GLOBAL(P1_CLK), !GLOBAL(U1L6), , !N1L64, , );


--P1_CLK is FREDEVIDER2:inst13|CLK at LC_X8_Y6_N2
--operation mode is normal

P1_CLK_lut_out = !P1_CLK;
P1_CLK = DFFEA(P1_CLK_lut_out, M1_RD, VCC, , , , );


--N1L64 is VOLTAGE_CONV:inst12|LessThan~8 at LC_X9_Y7_N7
--operation mode is normal

N1L64_carry_eqn = (!N1L43 & N1L44) # (N1L43 & N1L54);
N1L64 = N1L71 & N1L64_carry_eqn & W2_q_b[7] # !N1L71 & (N1L64_carry_eqn # W2_q_b[7]);


--N2L71 is VOLTAGE_CONV:inst15|add~8 at LC_X17_Y6_N7
--operation mode is normal

N2L71_carry_eqn = (!N2L01 & N2L56) # (N2L01 & N2L66);
N2L71 = G1_RAMTMP2[7] $ N2L71_carry_eqn $ W1_q_b[7];

--N2_TEMP[7] is VOLTAGE_CONV:inst15|TEMP[7] at LC_X17_Y6_N7
--operation mode is normal

N2_TEMP[7] = DFFEA(N2L71, !GLOBAL(P1_CLK), !GLOBAL(U1L6), , !N2L64, , );


--N2L64 is VOLTAGE_CONV:inst15|LessThan~8 at LC_X18_Y6_N7
--operation mode is normal

N2L64_carry_eqn = (!N2L43 & N2L44) # (N2L43 & N2L54);
N2L64 = W1_q_b[7] & (N2L64_carry_eqn # !N2L71) # !W1_q_b[7] & N2L64_carry_eqn & !N2L71;


--F1_REG_Q[21] is generator_accB:inst4|REG_Q[21] at LC_X18_Y5_N3
--operation mode is normal

F1_REG_Q[21]_lut_out = F1L57 & (F1L99 # !F1L37);
F1_REG_Q[21] = DFFEA(F1_REG_Q[21]_lut_out, GLOBAL(K1_CLK), !G1_TMP, , , , );


--G1_TMP is BUS_1:inst5|TMP at LC_X16_Y2_N7
--operation mode is normal

G1_TMP_lut_out = Y1_q_a[3] & (G1_TMP # G1_LATCH_ADDRES[1] & G1L101) # !Y1_q_a[3] & G1_LATCH_ADDRES[1] & G1L101;
G1_TMP = DFFEA(G1_TMP_lut_out, !GLOBAL(CLK), VCC, , G1L92, , );


--Y1_q_a[2] is BUS_1:inst5|altsyncram:reduce_or_rtl_1|altsyncram_7vi:auto_generated|q_a[2] at M4K_X13_Y2
--RAM Block Operation Mode: ROM
--Port A Depth: 256, Port A Width: 8
--Port A Logical Depth: 256, Port A Logical Width: 8
--Port A Input: Registered, Port A Output: Un-registered
Y1_q_a[2]_PORT_A_address = BUS(A1L34, A1L44, A1L54, A1L64, A1L74, A1L84, A1L94, A1L24);
Y1_q_a[2]_PORT_A_address_reg = DFFE(Y1_q_a[2]_PORT_A_address, Y1_q_a[2]_clock_0, , , );
Y1_q_a[2]_clock_0 = !GLOBAL(ALE);
Y1_q_a[2]_PORT_A_data_out = MEMORY(, , Y1_q_a[2]_PORT_A_address_reg, , , , , , Y1_q_a[2]_clock_0, , , , , );
Y1_q_a[2] = Y1_q_a[2]_PORT_A_data_out[0];

--Y1_q_a[4] is BUS_1:inst5|altsyncram:reduce_or_rtl_1|altsyncram_7vi:auto_generated|q_a[4] at M4K_X13_Y2
Y1_q_a[2]_PORT_A_address = BUS(A1L34, A1L44, A1L54, A1L64, A1L74, A1L84, A1L94, A1L24);
Y1_q_a[2]_PORT_A_address_reg = DFFE(Y1_q_a[2]_PORT_A_address, Y1_q_a[2]_clock_0, , , );
Y1_q_a[2]_clock_0 = !GLOBAL(ALE);
Y1_q_a[2]_PORT_A_data_out = MEMORY(, , Y1_q_a[2]_PORT_A_address_reg, , , , , , Y1_q_a[2]_clock_0, , , , , );
Y1_q_a[4] = Y1_q_a[2]_PORT_A_data_out[7];

--Y1_q_a[7] is BUS_1:inst5|altsyncram:reduce_or_rtl_1|altsyncram_7vi:auto_generated|q_a[7] at M4K_X13_Y2
Y1_q_a[2]_PORT_A_address = BUS(A1L34, A1L44, A1L54, A1L64, A1L74, A1L84, A1L94, A1L24);
Y1_q_a[2]_PORT_A_address_reg = DFFE(Y1_q_a[2]_PORT_A_address, Y1_q_a[2]_clock_0, , , );
Y1_q_a[2]_clock_0 = !GLOBAL(ALE);
Y1_q_a[2]_PORT_A_data_out = MEMORY(, , Y1_q_a[2]_PORT_A_address_reg, , , , , , Y1_q_a[2]_clock_0, , , , , );
Y1_q_a[7] = Y1_q_a[2]_PORT_A_data_out[6];

--Y1_q_a[1] is BUS_1:inst5|altsyncram:reduce_or_rtl_1|altsyncram_7vi:auto_generated|q_a[1] at M4K_X13_Y2
Y1_q_a[2]_PORT_A_address = BUS(A1L34, A1L44, A1L54, A1L64, A1L74, A1L84, A1L94, A1L24);
Y1_q_a[2]_PORT_A_address_reg = DFFE(Y1_q_a[2]_PORT_A_address, Y1_q_a[2]_clock_0, , , );
Y1_q_a[2]_clock_0 = !GLOBAL(ALE);
Y1_q_a[2]_PORT_A_data_out = MEMORY(, , Y1_q_a[2]_PORT_A_address_reg, , , , , , Y1_q_a[2]_clock_0, , , , , );
Y1_q_a[1] = Y1_q_a[2]_PORT_A_data_out[5];

--Y1_q_a[0] is BUS_1:inst5|altsyncram:reduce_or_rtl_1|altsyncram_7vi:auto_generated|q_a[0] at M4K_X13_Y2
Y1_q_a[2]_PORT_A_address = BUS(A1L34, A1L44, A1L54, A1L64, A1L74, A1L84, A1L94, A1L24);
Y1_q_a[2]_PORT_A_address_reg = DFFE(Y1_q_a[2]_PORT_A_address, Y1_q_a[2]_clock_0, , , );
Y1_q_a[2]_clock_0 = !GLOBAL(ALE);
Y1_q_a[2]_PORT_A_data_out = MEMORY(, , Y1_q_a[2]_PORT_A_address_reg, , , , , , Y1_q_a[2]_clock_0, , , , , );
Y1_q_a[0] = Y1_q_a[2]_PORT_A_data_out[4];

--Y1_q_a[6] is BUS_1:inst5|altsyncram:reduce_or_rtl_1|altsyncram_7vi:auto_generated|q_a[6] at M4K_X13_Y2
Y1_q_a[2]_PORT_A_address = BUS(A1L34, A1L44, A1L54, A1L64, A1L74, A1L84, A1L94, A1L24);
Y1_q_a[2]_PORT_A_address_reg = DFFE(Y1_q_a[2]_PORT_A_address, Y1_q_a[2]_clock_0, , , );
Y1_q_a[2]_clock_0 = !GLOBAL(ALE);
Y1_q_a[2]_PORT_A_data_out = MEMORY(, , Y1_q_a[2]_PORT_A_address_reg, , , , , , Y1_q_a[2]_clock_0, , , , , );
Y1_q_a[6] = Y1_q_a[2]_PORT_A_data_out[3];

--Y1_q_a[5] is BUS_1:inst5|altsyncram:reduce_or_rtl_1|altsyncram_7vi:auto_generated|q_a[5] at M4K_X13_Y2
Y1_q_a[2]_PORT_A_address = BUS(A1L34, A1L44, A1L54, A1L64, A1L74, A1L84, A1L94, A1L24);
Y1_q_a[2]_PORT_A_address_reg = DFFE(Y1_q_a[2]_PORT_A_address, Y1_q_a[2]_clock_0, , , );
Y1_q_a[2]_clock_0 = !GLOBAL(ALE);
Y1_q_a[2]_PORT_A_data_out = MEMORY(, , Y1_q_a[2]_PORT_A_address_reg, , , , , , Y1_q_a[2]_clock_0, , , , , );
Y1_q_a[5] = Y1_q_a[2]_PORT_A_data_out[2];

--Y1_q_a[3] is BUS_1:inst5|altsyncram:reduce_or_rtl_1|altsyncram_7vi:auto_generated|q_a[3] at M4K_X13_Y2
Y1_q_a[2]_PORT_A_address = BUS(A1L34, A1L44, A1L54, A1L64, A1L74, A1L84, A1L94, A1L24);
Y1_q_a[2]_PORT_A_address_reg = DFFE(Y1_q_a[2]_PORT_A_address, Y1_q_a[2]_clock_0, , , );
Y1_q_a[2]_clock_0 = !GLOBAL(ALE);
Y1_q_a[2]_PORT_A_data_out = MEMORY(, , Y1_q_a[2]_PORT_A_address_reg, , , , , , Y1_q_a[2]_clock_0, , , , , );
Y1_q_a[3] = Y1_q_a[2]_PORT_A_data_out[1];


--G1_LATCH_ADDRES[5] is BUS_1:inst5|LATCH_ADDRES[5] at LC_X16_Y2_N8
--operation mode is normal

G1_LATCH_ADDRES[5]_sload_eqn = A1L44;
G1_LATCH_ADDRES[5] = DFFEA(G1_LATCH_ADDRES[5]_sload_eqn, !GLOBAL(ALE), VCC, , , , );


--G1_LATCH_ADDRES[4] is BUS_1:inst5|LATCH_ADDRES[4] at LC_X16_Y2_N9
--operation mode is normal

G1_LATCH_ADDRES[4]_sload_eqn = A1L54;
G1_LATCH_ADDRES[4] = DFFEA(G1_LATCH_ADDRES[4]_sload_eqn, !GLOBAL(ALE), VCC, , , , );


--G1_LATCH_ADDRES[7] is BUS_1:inst5|LATCH_ADDRES[7] at LC_X16_Y2_N6
--operation mode is normal

G1_LATCH_ADDRES[7]_lut_out = A1L24;
G1_LATCH_ADDRES[7] = DFFEA(G1_LATCH_ADDRES[7]_lut_out, !GLOBAL(ALE), VCC, , , , );


--G1L99 is BUS_1:inst5|reduce_nor~170 at LC_X16_Y2_N0
--operation mode is normal

G1_LATCH_ADDRES[6]_qfbk = G1_LATCH_ADDRES[6];
G1L99 = G1_LATCH_ADDRES[4] & G1_LATCH_ADDRES[5] & G1_LATCH_ADDRES[6]_qfbk & G1_LATCH_ADDRES[7];

--G1_LATCH_ADDRES[6] is BUS_1:inst5|LATCH_ADDRES[6] at LC_X16_Y2_N0
--operation mode is normal

G1_LATCH_ADDRES[6]_sload_eqn = A1L34;
G1_LATCH_ADDRES[6] = DFFEA(G1_LATCH_ADDRES[6]_sload_eqn, !GLOBAL(ALE), VCC, , , , );


--G1L001 is BUS_1:inst5|reduce_nor~171 at LC_X18_Y2_N5
--operation mode is normal

G1_LATCH_ADDRES[1]_qfbk = G1_LATCH_ADDRES[1];
G1L001 = !G1_LATCH_ADDRES[2] & G1_LATCH_ADDRES[1]_qfbk & G1L99;

--G1_LATCH_ADDRES[1] is BUS_1:inst5|LATCH_ADDRES[1] at LC_X18_Y2_N5
--operation mode is normal

G1_LATCH_ADDRES[1]_sload_eqn = A1L84;
G1_LATCH_ADDRES[1] = DFFEA(G1_LATCH_ADDRES[1]_sload_eqn, !GLOBAL(ALE), VCC, , , , );


--G1L49 is BUS_1:inst5|reduce_nor~3 at LC_X18_Y2_N8
--operation mode is normal

G1_LATCH_ADDRES[0]_qfbk = G1_LATCH_ADDRES[0];
G1L49 = !G1_LATCH_ADDRES[3] & G1_LATCH_ADDRES[0]_qfbk & G1L001;

--G1_LATCH_ADDRES[0] is BUS_1:inst5|LATCH_ADDRES[0] at LC_X18_Y2_N8
--operation mode is normal

G1_LATCH_ADDRES[0]_sload_eqn = A1L94;
G1_LATCH_ADDRES[0] = DFFEA(G1_LATCH_ADDRES[0]_sload_eqn, !GLOBAL(ALE), VCC, , , , );


--G1L92 is BUS_1:inst5|process2~0 at LC_X19_Y3_N5
--operation mode is normal

G1L92 = !WR & !CS;


--F1L16 is generator_accB:inst4|add~18 at LC_X16_Y5_N1
--operation mode is arithmetic

F1L16_carry_eqn = (!F1L65 & F1L95) # (F1L65 & F1L06);
F1L16 = F1_REG_Q[17] $ F1L16_carry_eqn;

--F1L36 is generator_accB:inst4|add~18COUT0 at LC_X16_Y5_N1
--operation mode is arithmetic

F1L36_cout_0 = !F1L95 # !F1_REG_Q[17];
F1L36 = CARRY(F1L36_cout_0);

--F1L46 is generator_accB:inst4|add~18COUT1 at LC_X16_Y5_N1
--operation mode is arithmetic

F1L46_cout_1 = !F1L06 # !F1_REG_Q[17];
F1L46 = CARRY(F1L46_cout_1);


--F1L56 is generator_accB:inst4|add~19 at LC_X16_Y5_N2
--operation mode is arithmetic

F1L56_carry_eqn = (!F1L65 & F1L36) # (F1L65 & F1L46);
F1L56 = F1_REG_Q[18] $ !F1L56_carry_eqn;

--F1L76 is generator_accB:inst4|add~19COUT0 at LC_X16_Y5_N2
--operation mode is arithmetic

F1L76_cout_0 = F1_REG_Q[18] & !F1L36;
F1L76 = CARRY(F1L76_cout_0);

--F1L86 is generator_accB:inst4|add~19COUT1 at LC_X16_Y5_N2
--operation mode is arithmetic

F1L86_cout_1 = F1_REG_Q[18] & !F1L46;
F1L86 = CARRY(F1L86_cout_1);


--F1L96 is generator_accB:inst4|add~20 at LC_X16_Y5_N3
--operation mode is arithmetic

F1L96_carry_eqn = (!F1L65 & F1L76) # (F1L65 & F1L86);
F1L96 = F1_REG_Q[19] $ F1L96_carry_eqn;

--F1L17 is generator_accB:inst4|add~20COUT0 at LC_X16_Y5_N3
--operation mode is arithmetic

F1L17_cout_0 = !F1L76 # !F1_REG_Q[19];
F1L17 = CARRY(F1L17_cout_0);

--F1L27 is generator_accB:inst4|add~20COUT1 at LC_X16_Y5_N3
--operation mode is arithmetic

F1L27_cout_1 = !F1L86 # !F1_REG_Q[19];
F1L27 = CARRY(F1L27_cout_1);


--F1L99 is generator_accB:inst4|REG_Q~538 at LC_X16_Y5_N9
--operation mode is normal

F1L99 = !F1L96 & !F1L56 & !F1L16;


--F1L37 is generator_accB:inst4|add~21 at LC_X16_Y5_N4
--operation mode is arithmetic

F1L37_carry_eqn = (!F1L65 & F1L17) # (F1L65 & F1L27);
F1L37 = F1_REG_Q[20] $ !F1L37_carry_eqn;

--F1L47 is generator_accB:inst4|add~21COUT at LC_X16_Y5_N4
--operation mode is arithmetic

F1L47 = CARRY(F1_REG_Q[20] & !F1L27);


--F1L57 is generator_accB:inst4|add~22 at LC_X16_Y5_N5
--operation mode is normal

F1L57_carry_eqn = F1L47;
F1L57 = F1L57_carry_eqn $ F1_REG_Q[21];


--F1L201 is generator_accB:inst4|TEMP~0 at LC_X16_Y5_N6
--operation mode is normal

F1L201 = !F1L99 & !G1_TMP & F1L37 & F1L57;


--N1L51 is VOLTAGE_CONV:inst12|add~7 at LC_X10_Y7_N6
--operation mode is arithmetic

N1L51_carry_eqn = (!N1L01 & N1L26) # (N1L01 & N1L36);
N1L51 = G1_RAMTMP5[6] $ W2_q_b[6] $ !N1L51_carry_eqn;

--N1_TEMP[6] is VOLTAGE_CONV:inst12|TEMP[6] at LC_X10_Y7_N6
--operation mode is arithmetic

N1_TEMP[6] = DFFEA(N1L51, !GLOBAL(P1_CLK), !GLOBAL(U1L6), , !N1L64, , );

--N1L56 is VOLTAGE_CONV:inst12|TEMP[6]~COUT0 at LC_X10_Y7_N6
--operation mode is arithmetic

N1L56_cout_0 = G1_RAMTMP5[6] & (W2_q_b[6] # !N1L26) # !G1_RAMTMP5[6] & W2_q_b[6] & !N1L26;
N1L56 = CARRY(N1L56_cout_0);

--N1L66 is VOLTAGE_CONV:inst12|TEMP[6]~COUT1 at LC_X10_Y7_N6
--operation mode is arithmetic

N1L66_cout_1 = G1_RAMTMP5[6] & (W2_q_b[6] # !N1L36) # !G1_RAMTMP5[6] & W2_q_b[6] & !N1L36;
N1L66 = CARRY(N1L66_cout_1);


--N2L51 is VOLTAGE_CONV:inst15|add~7 at LC_X17_Y6_N6
--operation mode is arithmetic

N2L51_carry_eqn = (!N2L01 & N2L26) # (N2L01 & N2L36);
N2L51 = G1_RAMTMP2[6] $ W1_q_b[6] $ !N2L51_carry_eqn;

--N2_TEMP[6] is VOLTAGE_CONV:inst15|TEMP[6] at LC_X17_Y6_N6