wave.fit.eqn

数字示波器的FPGA实现 VHDL编写 Quartus7.1测试通过

--M1_RD is MAX114:inst11|RD at LC_X8_Y6_N6
--operation mode is normal

M1_RD_lut_out = !M1_cnt[1] & !M1_cnt[2] & !M1_cnt[0];
M1_RD = DFFEA(M1_RD_lut_out, GLOBAL(CLK), VCC, , M1L82, , );


--M1_B is MAX114:inst11|B at LC_X8_Y7_N2
--operation mode is normal

M1_B_lut_out = !M1_cnt[2] & M1_cnt[3] & !M1_cnt[0] & M1_cnt[1];
M1_B = DFFEA(M1_B_lut_out, GLOBAL(CLK), VCC, , M1L92, , );


--E1_TEMP is DA5180:inst3|TEMP at LC_X17_Y8_N2
--operation mode is normal

E1_TEMP_lut_out = !E1_TEMP;
E1_TEMP = DFFEA(E1_TEMP_lut_out, !GLOBAL(K1_CLK), VCC, , E1_cnt[0], , );


--E1_DD[9] is DA5180:inst3|DD[9] at LC_X18_Y5_N0
--operation mode is normal

E1_DD[9]_lut_out = R1L1 & N2_TEMP[7] # !R1L1 & N1_TEMP[7];
E1_DD[9]_sload_eqn = (!E1_TEMP & J1_TEMP_Q_1[9]) # (E1_TEMP & E1_DD[9]_lut_out);
E1_DD[9] = DFFEA(E1_DD[9]_sload_eqn, !GLOBAL(K1_CLK), VCC, , !E1_cnt[0], , );


--E1_DD[8] is DA5180:inst3|DD[8] at LC_X18_Y5_N6
--operation mode is normal

E1_DD[8]_lut_out = R1L1 & N2_TEMP[6] # !R1L1 & N1_TEMP[6];
E1_DD[8]_sload_eqn = (!E1_TEMP & J1_TEMP_Q_1[8]) # (E1_TEMP & E1_DD[8]_lut_out);
E1_DD[8] = DFFEA(E1_DD[8]_sload_eqn, !GLOBAL(K1_CLK), VCC, , !E1_cnt[0], , );


--E1_DD[7] is DA5180:inst3|DD[7] at LC_X15_Y4_N1
--operation mode is normal

E1_DD[7]_lut_out = N2_TEMP[5] & (N1_TEMP[5] # R1L1) # !N2_TEMP[5] & N1_TEMP[5] & !R1L1;
E1_DD[7]_sload_eqn = (!E1_TEMP & J1_TEMP_Q_1[7]) # (E1_TEMP & E1_DD[7]_lut_out);
E1_DD[7] = DFFEA(E1_DD[7]_sload_eqn, !GLOBAL(K1_CLK), VCC, , !E1_cnt[0], , );


--E1_DD[6] is DA5180:inst3|DD[6] at LC_X15_Y4_N0
--operation mode is normal

E1_DD[6]_lut_out = N1_TEMP[4] & (N2_TEMP[4] # !R1L1) # !N1_TEMP[4] & N2_TEMP[4] & R1L1;
E1_DD[6]_sload_eqn = (!E1_TEMP & J1_TEMP_Q_1[6]) # (E1_TEMP & E1_DD[6]_lut_out);
E1_DD[6] = DFFEA(E1_DD[6]_sload_eqn, !GLOBAL(K1_CLK), VCC, , !E1_cnt[0], , );


--E1_DD[5] is DA5180:inst3|DD[5] at LC_X18_Y5_N9
--operation mode is normal

E1_DD[5]_lut_out = N1_TEMP[3] & (N2_TEMP[3] # !R1L1) # !N1_TEMP[3] & N2_TEMP[3] & R1L1;
E1_DD[5]_sload_eqn = (!E1_TEMP & J1_TEMP_Q_1[5]) # (E1_TEMP & E1_DD[5]_lut_out);
E1_DD[5] = DFFEA(E1_DD[5]_sload_eqn, !GLOBAL(K1_CLK), VCC, , !E1_cnt[0], , );


--E1_DD[4] is DA5180:inst3|DD[4] at LC_X18_Y7_N2
--operation mode is normal

E1_DD[4]_lut_out = N1_TEMP[2] & (N2_TEMP[2] # !R1L1) # !N1_TEMP[2] & N2_TEMP[2] & R1L1;
E1_DD[4]_sload_eqn = (!E1_TEMP & J1_TEMP_Q_1[4]) # (E1_TEMP & E1_DD[4]_lut_out);
E1_DD[4] = DFFEA(E1_DD[4]_sload_eqn, !GLOBAL(K1_CLK), VCC, , !E1_cnt[0], , );


--E1_DD[3] is DA5180:inst3|DD[3] at LC_X18_Y5_N5
--operation mode is normal

E1_DD[3]_lut_out = N1_TEMP[1] & (N2_TEMP[1] # !R1L1) # !N1_TEMP[1] & N2_TEMP[1] & R1L1;
E1_DD[3]_sload_eqn = (!E1_TEMP & J1_TEMP_Q_1[3]) # (E1_TEMP & E1_DD[3]_lut_out);
E1_DD[3] = DFFEA(E1_DD[3]_sload_eqn, !GLOBAL(K1_CLK), VCC, , !E1_cnt[0], , );


--E1_DD[2] is DA5180:inst3|DD[2] at LC_X18_Y8_N2
--operation mode is normal

E1_DD[2]_lut_out = N2_TEMP[0] & (N1_TEMP[0] # R1L1) # !N2_TEMP[0] & N1_TEMP[0] & !R1L1;
E1_DD[2]_sload_eqn = (!E1_TEMP & J1_TEMP_Q_1[2]) # (E1_TEMP & E1_DD[2]_lut_out);
E1_DD[2] = DFFEA(E1_DD[2]_sload_eqn, !GLOBAL(K1_CLK), VCC, , !E1_cnt[0], , );


--E1_DD[1] is DA5180:inst3|DD[1] at LC_X16_Y9_N4
--operation mode is normal

E1_DD[1]_lut_out = J1_TEMP_Q_1[1] & !E1_TEMP;
E1_DD[1] = DFFEA(E1_DD[1]_lut_out, !GLOBAL(K1_CLK), VCC, , !E1_cnt[0], , );


--E1_DD[0] is DA5180:inst3|DD[0] at LC_X16_Y9_N6
--operation mode is normal

E1_DD[0]_lut_out = J1_TEMP_Q_1[0] & !E1_TEMP;
E1_DD[0] = DFFEA(E1_DD[0]_lut_out, !GLOBAL(K1_CLK), VCC, , !E1_cnt[0], , );


--M1_cnt[1] is MAX114:inst11|cnt[1] at LC_X8_Y9_N4
--operation mode is normal

M1_cnt[1]_lut_out = M1_cnt[0] & !M1_cnt[1] & (INTN # M1_cnt[2]) # !M1_cnt[0] & M1_cnt[1];
M1_cnt[1] = DFFEA(M1_cnt[1]_lut_out, GLOBAL(CLK), VCC, , , , );


--M1_cnt[2] is MAX114:inst11|cnt[2] at LC_X8_Y9_N5
--operation mode is normal

M1_cnt[2]_lut_out = !M1_cnt[2];
M1_cnt[2] = DFFEA(M1_cnt[2]_lut_out, GLOBAL(CLK), VCC, , M1L1, , );


--M1_cnt[0] is MAX114:inst11|cnt[0] at LC_X8_Y9_N1
--operation mode is normal

M1_cnt[0]_lut_out = M1_cnt[0] & !INTN & !M1_cnt[1] & !M1_cnt[2] # !M1_cnt[0] & (M1_cnt[2] # !M1_cnt[1] # !INTN);
M1_cnt[0] = DFFEA(M1_cnt[0]_lut_out, GLOBAL(CLK), VCC, , , , );


--M1L82 is MAX114:inst11|Mux~318 at LC_X8_Y9_N3
--operation mode is normal

M1L82 = !M1_cnt[0] & !M1_cnt[2];


--M1_cnt[3] is MAX114:inst11|cnt[3] at LC_X8_Y7_N4
--operation mode is normal

M1_cnt[3]_lut_out = !M1_cnt[3];
M1_cnt[3] = DFFEA(M1_cnt[3]_lut_out, GLOBAL(CLK), VCC, , M1L03, , );


--M1L92 is MAX114:inst11|Mux~319 at LC_X8_Y9_N2
--operation mode is normal

M1L92 = !M1_cnt[0] & M1_cnt[1] & !M1_cnt[2];


--K1_CLK is FREDEVIDER8:inst8|CLK at LC_X10_Y6_N8
--operation mode is normal

K1_CLK_lut_out = !K1_CLK;
K1_CLK = DFFEA(K1_CLK_lut_out, GLOBAL(CLK), VCC, , K1L6, , );


--E1_cnt[0] is DA5180:inst3|cnt[0] at LC_X17_Y8_N4
--operation mode is normal

E1_cnt[0]_lut_out = !E1_cnt[0];
E1_cnt[0] = DFFEA(E1_cnt[0]_lut_out, !GLOBAL(K1_CLK), VCC, , , , );


--J1_TEMP_Q_1[9] is generator_reg81:inst7|TEMP_Q_1[9] at LC_X18_Y5_N4
--operation mode is normal

J1_TEMP_Q_1[9]_lut_out = F1_REG_Q[21];
J1_TEMP_Q_1[9] = DFFEA(J1_TEMP_Q_1[9]_lut_out, GLOBAL(K1_CLK), !G1_TMP, , , , );


--G1_RAMTMP0[0] is BUS_1:inst5|RAMTMP0[0] at LC_X19_Y2_N3
--operation mode is normal

G1_RAMTMP0[0]_lut_out = Y1_q_a[2] & (G1_RAMTMP0[0] # A1L94 & G1L49) # !Y1_q_a[2] & A1L94 & G1L49;
G1_RAMTMP0[0] = DFFEA(G1_RAMTMP0[0]_lut_out, !GLOBAL(CLK), VCC, , G1L92, , );


--F1_TEMP is generator_accB:inst4|TEMP at LC_X16_Y5_N7
--operation mode is normal

F1_TEMP_lut_out = !F1_TEMP;
F1_TEMP = DFFEA(F1_TEMP_lut_out, GLOBAL(K1_CLK), VCC, , F1L201, , );


--G1_RAMTMP0[1] is BUS_1:inst5|RAMTMP0[1] at LC_X19_Y2_N0
--operation mode is normal

G1_RAMTMP0[1]_lut_out = G1L49 & (A1L84 # G1_RAMTMP0[1] & Y1_q_a[2]) # !G1L49 & G1_RAMTMP0[1] & Y1_q_a[2];
G1_RAMTMP0[1] = DFFEA(G1_RAMTMP0[1]_lut_out, !GLOBAL(CLK), VCC, , G1L92, , );


--R1L1 is MUX2_3:inst17|Q[9]~64 at LC_X18_Y5_N1
--operation mode is normal

R1L1 = G1_RAMTMP0[0] & (F1_TEMP # !G1_RAMTMP0[1]);


--J1_TEMP_Q_1[8] is generator_reg81:inst7|TEMP_Q_1[8] at LC_X18_Y5_N8
--operation mode is normal

J1_TEMP_Q_1[8]_lut_out = F1_REG_Q[20];
J1_TEMP_Q_1[8] = DFFEA(J1_TEMP_Q_1[8]_lut_out, GLOBAL(K1_CLK), !G1_TMP, , , , );


--J1_TEMP_Q_1[7] is generator_reg81:inst7|TEMP_Q_1[7] at LC_X15_Y4_N8
--operation mode is normal

J1_TEMP_Q_1[7]_lut_out = F1_REG_Q[19];
J1_TEMP_Q_1[7] = DFFEA(J1_TEMP_Q_1[7]_lut_out, GLOBAL(K1_CLK), !G1_TMP, , , , );


--J1_TEMP_Q_1[6] is generator_reg81:inst7|TEMP_Q_1[6] at LC_X15_Y4_N7
--operation mode is normal

J1_TEMP_Q_1[6]_lut_out = F1_REG_Q[18];
J1_TEMP_Q_1[6] = DFFEA(J1_TEMP_Q_1[6]_lut_out, GLOBAL(K1_CLK), !G1_TMP, , , , );


--J1_TEMP_Q_1[5] is generator_reg81:inst7|TEMP_Q_1[5] at LC_X18_Y5_N7
--operation mode is normal

J1_TEMP_Q_1[5]_lut_out = F1_REG_Q[17];
J1_TEMP_Q_1[5] = DFFEA(J1_TEMP_Q_1[5]_lut_out, GLOBAL(K1_CLK), !G1_TMP, , , , );


--J1_TEMP_Q_1[4] is generator_reg81:inst7|TEMP_Q_1[4] at LC_X18_Y7_N4
--operation mode is normal

J1_TEMP_Q_1[4]_lut_out = F1_REG_Q[16];
J1_TEMP_Q_1[4] = DFFEA(J1_TEMP_Q_1[4]_lut_out, GLOBAL(K1_CLK), !G1_TMP, , , , );


--J1_TEMP_Q_1[3] is generator_reg81:inst7|TEMP_Q_1[3] at LC_X17_Y7_N7
--operation mode is normal

J1_TEMP_Q_1[3]_sload_eqn = F1_REG_Q[15];
J1_TEMP_Q_1[3] = DFFEA(J1_TEMP_Q_1[3]_sload_eqn, GLOBAL(K1_CLK), !G1_TMP, , , , );


--J1_TEMP_Q_1[2] is generator_reg81:inst7|TEMP_Q_1[2] at LC_X18_Y8_N4
--operation mode is normal

J1_TEMP_Q_1[2]_lut_out = F1_REG_Q[14];
J1_TEMP_Q_1[2] = DFFEA(J1_TEMP_Q_1[2]_lut_out, GLOBAL(K1_CLK), !G1_TMP, , , , );


--J1_TEMP_Q_1[1] is generator_reg81:inst7|TEMP_Q_1[1] at LC_X16_Y9_N3
--operation mode is normal

J1_TEMP_Q_1[1]_sload_eqn = F1_REG_Q[13];
J1_TEMP_Q_1[1] = DFFEA(J1_TEMP_Q_1[1]_sload_eqn, GLOBAL(K1_CLK), !G1_TMP, , , , );


--J1_TEMP_Q_1[0] is generator_reg81:inst7|TEMP_Q_1[0] at LC_X16_Y9_N2
--operation mode is normal

J1_TEMP_Q_1[0]_sload_eqn = F1_REG_Q[12];
J1_TEMP_Q_1[0] = DFFEA(J1_TEMP_Q_1[0]_sload_eqn, GLOBAL(K1_CLK), !G1_TMP, , , , );


--M1L1 is MAX114:inst11|add~56 at LC_X8_Y9_N6
--operation mode is normal

M1L1 = M1_cnt[1] & M1_cnt[0];


--M1L03 is MAX114:inst11|Mux~321 at LC_X8_Y9_N7
--operation mode is normal

M1L03 = M1_cnt[0] & M1_cnt[1] & M1_cnt[2];


--K1_COUNTER[1] is FREDEVIDER8:inst8|COUNTER[1] at LC_X10_Y6_N3
--operation mode is normal

K1_COUNTER[1]_lut_out = K1_COUNTER[0] & !K1_COUNTER[2] & !K1_COUNTER[1] # !K1_COUNTER[0] & K1_COUNTER[1];
K1_COUNTER[1] = DFFEA(K1_COUNTER[1]_lut_out, GLOBAL(CLK), VCC, , , , );


--K1_COUNTER[0] is FREDEVIDER8:inst8|COUNTER[0] at LC_X10_Y6_N5
--operation mode is normal

K1_COUNTER[0]_lut_out = !K1_COUNTER[0];
K1_COUNTER[0] = DFFEA(K1_COUNTER[0]_lut_out, GLOBAL(CLK), VCC, , , , );


--K1_COUNTER[2] is FREDEVIDER8:inst8|COUNTER[2] at LC_X10_Y6_N4
--operation mode is normal

K1_COUNTER[2]_lut_out = K1_COUNTER[0] & !K1_COUNTER[2] & K1_COUNTER[1] # !K1_COUNTER[0] & K1_COUNTER[2];
K1_COUNTER[2] = DFFEA(K1_COUNTER[2]_lut_out, GLOBAL(CLK), VCC, , , , );


--K1L6 is FREDEVIDER8:inst8|reduce_nor~14 at LC_X10_Y6_N6
--operation mode is normal

K1L6 = K1_COUNTER[0] & K1_COUNTER[2] & !K1_COUNTER[1];


--N1L71 is VOLTAGE_CONV:inst12|add~8 at LC_X10_Y7_N7
--operation mode is normal

N1L71_carry_eqn = (!N1L01 & N1L56) # (N1L01 & N1L66);
N1L71 = G1_RAMTMP5[7] $ N1L71_carry_eqn $ W2_q_b[7];

--N1_TEMP[7] is VOLTAGE_CONV:inst12|TEMP[7] at LC_X10_Y7_N7
--operation mode is normal