wave.tan.rpt
来自「数字示波器的FPGA实现 VHDL编写 Quartus7.1测试通过」· RPT 代码 · 共 229 行 · 第 1/5 页
RPT
229 行
+-----------------+--------------------+----------+------------------+----------+-----------------------+---------------------+--------+
; CLK ; ; User Pin ; NONE ; NONE ; N/A ; N/A ; N/A ;
; ALE ; ; User Pin ; NONE ; NONE ; N/A ; N/A ; N/A ;
; CLK2 ; ; User Pin ; NONE ; NONE ; N/A ; N/A ; N/A ;
+-----------------+--------------------+----------+------------------+----------+-----------------------+---------------------+--------+
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Setup: 'CLK' ;
+-----------------------------------------+-----------------------------------------------------+-------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; Slack ; Actual fmax (period) ; From ; To ; From Clock ; To Clock ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
+-----------------------------------------+-----------------------------------------------------+-------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; N/A ; 60.31 MHz ( period = 16.580 ns ) ; GET_RDADDR:inst10|COUNTER[9] ; dram:inst14|altsyncram:altsyncram_component|altsyncram_3771:auto_generated|ram_block1a3~portb_address_reg9 ; CLK ; CLK ; None ; None ; None ;
; N/A ; 60.55 MHz ( period = 16.516 ns ) ; GET_RDADDR:inst10|COUNTER[7] ; dram:inst14|altsyncram:altsyncram_component|altsyncram_3771:auto_generated|ram_block1a3~portb_address_reg7 ; CLK ; CLK ; None ; None ; None ;
; N/A ; 61.09 MHz ( period = 16.370 ns ) ; GET_RDADDR:inst10|COUNTER[6] ; dram:inst14|altsyncram:altsyncram_component|altsyncram_3771:auto_generated|ram_block1a3~portb_address_reg6 ; CLK ; CLK ; None ; None ; None ;
; N/A ; 63.27 MHz ( period = 15.806 ns ) ; GET_RDADDR:inst10|COUNTER[0] ; dram:inst|altsyncram:altsyncram_component|altsyncram_3771:auto_generated|ram_block1a7~portb_address_reg0 ; CLK ; CLK ; None ; None ; None ;
; N/A ; 63.33 MHz ( period = 15.790 ns ) ; GET_RDADDR:inst10|COUNTER[0] ; dram:inst|altsyncram:altsyncram_component|altsyncram_3771:auto_generated|ram_block1a1~portb_address_reg0 ; CLK ; CLK ; None ; None ; None ;
; N/A ; 63.43 MHz ( period = 15.766 ns ) ; GET_RDADDR:inst10|COUNTER[1] ; dram:inst|altsyncram:altsyncram_component|altsyncram_3771:auto_generated|ram_block1a7~portb_address_reg1 ; CLK ; CLK ; None ; None ; None ;
; N/A ; 63.44 MHz ( period = 15.762 ns ) ; GET_RDADDR:inst10|COUNTER[1] ; dram:inst|altsyncram:altsyncram_component|altsyncram_3771:auto_generated|ram_block1a3~portb_address_reg1 ; CLK ; CLK ; None ; None ; None ;
; N/A ; 63.48 MHz ( period = 15.754 ns ) ; GET_RDADDR:inst10|COUNTER[1] ; dram:inst|altsyncram:altsyncram_component|altsyncram_3771:auto_generated|ram_block1a1~portb_address_reg1 ; CLK ; CLK ; None ; None ; None ;
; N/A ; 63.48 MHz ( period = 15.752 ns ) ; GET_RDADDR:inst10|COUNTER[10] ; dram:inst|altsyncram:altsyncram_component|altsyncram_3771:auto_generated|ram_block1a7~portb_address_reg10 ; CLK ; CLK ; None ; None ; None ;
; N/A ; 63.52 MHz ( period = 15.742 ns ) ; GET_RDADDR:inst10|COUNTER[0] ; dram:inst|altsyncram:altsyncram_component|altsyncram_3771:auto_generated|ram_block1a3~portb_address_reg0 ; CLK ; CLK ; None ; None ; None ;
; N/A ; 63.69 MHz ( period = 15.702 ns ) ; GET_RDADDR:inst10|COUNTER[10] ; dram:inst|altsyncram:altsyncram_component|altsyncram_3771:auto_generated|ram_block1a3~portb_address_reg10 ; CLK ; CLK ; None ; None ; None ;
; N/A ; 63.71 MHz ( period = 15.696 ns ) ; GET_RDADDR:inst10|COUNTER[10] ; dram:inst|altsyncram:altsyncram_component|altsyncram_3771:auto_generated|ram_block1a1~portb_address_reg10 ; CLK ; CLK ; None ; None ; None ;
; N/A ; 63.73 MHz ( period = 15.692 ns ) ; GET_RDADDR:inst10|COUNTER[5] ; dram:inst|altsyncram:altsyncram_component|altsyncram_3771:auto_generated|ram_block1a3~portb_address_reg5 ; CLK ; CLK ; None ; None ; None ;
; N/A ; 63.73 MHz ( period = 15.692 ns ) ; GET_RDADDR:inst10|COUNTER[4] ; dram:inst|altsyncram:altsyncram_component|altsyncram_3771:auto_generated|ram_block1a3~portb_address_reg4 ; CLK ; CLK ; None ; None ; None ;
; N/A ; 63.73 MHz ( period = 15.692 ns ) ; GET_RDADDR:inst10|COUNTER[2] ; dram:inst|altsyncram:altsyncram_component|altsyncram_3771:auto_generated|ram_block1a7~portb_address_reg2 ; CLK ; CLK ; None ; None ; None ;
; N/A ; 63.81 MHz ( period = 15.672 ns ) ; GET_RDADDR:inst10|COUNTER[3] ; dram:inst|altsyncram:altsyncram_component|altsyncram_3771:auto_generated|ram_block1a7~portb_address_reg3 ; CLK ; CLK ; None ; None ; None ;
; N/A ; 63.82 MHz ( period = 15.668 ns ) ; GET_RDADDR:inst10|COUNTER[8] ; dram:inst|altsyncram:altsyncram_component|altsyncram_3771:auto_generated|ram_block1a1~portb_address_reg8 ; CLK ; CLK ; None ; None ; None ;
; N/A ; 63.82 MHz ( period = 15.668 ns ) ; GET_RDADDR:inst10|COUNTER[3] ; dram:inst|altsyncram:altsyncram_component|altsyncram_3771:auto_generated|ram_block1a3~portb_address_reg3 ; CLK ; CLK ; None ; None ; None ;
; N/A ; 63.85 MHz ( period = 15.662 ns ) ; GET_RDADDR:inst10|COUNTER[4] ; dram:inst14|altsyncram:altsyncram_component|altsyncram_3771:auto_generated|ram_block1a3~portb_address_reg4 ; CLK ; CLK ; None ; None ; None ;
; N/A ; 63.85 MHz ( period = 15.662 ns ) ; GET_RDADDR:inst10|COUNTER[1] ; dram:inst|altsyncram:altsyncram_component|altsyncram_3771:auto_generated|ram_block1a6~portb_address_reg1 ; CLK ; CLK ; None ; None ; None ;
; N/A ; 63.87 MHz ( period = 15.658 ns ) ; GET_RDADDR:inst10|COUNTER[3] ; dram:inst|altsyncram:altsyncram_component|altsyncram_3771:auto_generated|ram_block1a1~portb_address_reg3 ; CLK ; CLK ; None ; None ; None ;
; N/A ; 63.87 MHz ( period = 15.656 ns ) ; GET_RDADDR:inst10|COUNTER[5] ; dram:inst|altsyncram:altsyncram_component|altsyncram_3771:auto_generated|ram_block1a7~portb_address_reg5 ; CLK ; CLK ; None ; None ; None ;
; N/A ; 63.89 MHz ( period = 15.652 ns ) ; GET_RDADDR:inst10|COUNTER[4] ; dram:inst|altsyncram:altsyncram_component|altsyncram_3771:auto_generated|ram_block1a7~portb_address_reg4 ; CLK ; CLK ; None ; None ; None ;
; N/A ; 63.90 MHz ( period = 15.650 ns ) ; GET_RDADDR:inst10|COUNTER[10] ; dram:inst|altsyncram:altsyncram_component|altsyncram_3771:auto_generated|ram_block1a6~portb_address_reg10 ; CLK ; CLK ; None ; None ; None ;
; N/A ; 63.92 MHz ( period = 15.644 ns ) ; GET_RDADDR:inst10|COUNTER[4] ; dram:inst14|altsyncram:altsyncram_component|altsyncram_3771:auto_generated|ram_block1a7~portb_address_reg4 ; CLK ; CLK ; None ; None ; None ;
; N/A ; 63.94 MHz ( period = 15.640 ns ) ; GET_RDADDR:inst10|COUNTER[5] ; dram:inst|altsyncram:altsyncram_component|altsyncram_3771:auto_generated|ram_block1a1~portb_address_reg5 ; CLK ; CLK ; None ; None ; None ;
; N/A ; 63.95 MHz ( period = 15.638 ns ) ; GET_RDADDR:inst10|COUNTER[4] ; dram:inst|altsyncram:altsyncram_component|altsyncram_3771:auto_generated|ram_block1a1~portb_address_reg4 ; CLK ; CLK ; None ; None ; None ;
; N/A ; 63.97 MHz ( period = 15.632 ns ) ; GET_RDADDR:inst10|COUNTER[2] ; dram:inst|altsyncram:altsyncram_component|altsyncram_3771:auto_generated|ram_block1a1~portb_address_reg2 ; CLK ; CLK ; None ; None ; None ;
; N/A ; 64.00 MHz ( period = 15.624 ns ) ; GET_RDADDR:inst10|COUNTER[7] ; dram:inst14|altsyncram:altsyncram_component|altsyncram_3771:auto_generated|ram_block1a6~portb_address_reg7 ; CLK ; CLK ; None ; None ; None ;
; N/A ; 64.05 MHz ( period = 15.614 ns ) ; GET_RDADDR:inst10|COUNTER[9] ; dram:inst14|altsyncram:altsyncram_component|altsyncram_3771:auto_generated|ram_block1a6~portb_address_reg9 ; CLK ; CLK ; None ; None ; None ;
; N/A ; 64.05 MHz ( period = 15.614 ns ) ; GET_RDADDR:inst10|COUNTER[7] ; dram:inst14|altsyncram:altsyncram_component|altsyncram_3771:auto_generated|ram_block1a4~portb_address_reg7 ; CLK ; CLK ; None ; None ; None ;
; N/A ; 64.05 MHz ( period = 15.612 ns ) ; GET_RDADDR:inst10|COUNTER[9] ; dram:inst14|altsyncram:altsyncram_component|altsyncram_3771:auto_generated|ram_block1a7~portb_address_reg9 ; CLK ; CLK ; None ; None ; None ;
; N/A ; 64.06 MHz ( period = 15.610 ns ) ; GET_RDADDR:inst10|COUNTER[5] ; dram:inst14|altsyncram:altsyncram_component|altsyncram_3771:auto_generated|ram_block1a6~portb_address_reg5 ; CLK ; CLK ; None ; None ; None ;
; N/A ; 64.09 MHz ( period = 15.602 ns ) ; GET_RDADDR:inst10|COUNTER[2] ; dram:inst|altsyncram:altsyncram_component|altsyncram_3771:auto_generated|ram_block1a3~portb_address_reg2 ; CLK ; CLK ; None ; None ; None ;
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