wave.tan.rpt

数字示波器的FPGA实现 VHDL编写 Quartus7.1测试通过

+----------------------------------------------------------------------------------------+
; Timing Analyzer Settings                                                               ;
+-------------------------------------------------------+--------------------+------+----+
; Option                                                ; Setting            ; From ; To ;
+-------------------------------------------------------+--------------------+------+----+
; Device name                                           ; EP1C3T144C8        ;      ;    ;
; Timing Models                                         ; Production         ;      ;    ;
; Number of source nodes to report per destination node ; 10                 ;      ;    ;
; Number of destination nodes to report                 ; 10                 ;      ;    ;
; Number of paths to report                             ; 200                ;      ;    ;
; Run Minimum Analysis                                  ; On                 ;      ;    ;
; Use Minimum Timing Models                             ; Off                ;      ;    ;
; Report IO Paths Separately                            ; Off                ;      ;    ;
; Clock Analysis Only                                   ; Off                ;      ;    ;
; Default hold multicycle                               ; Same as Multicycle ;      ;    ;
; Cut paths between unrelated clock domains             ; On                 ;      ;    ;
; Cut off read during write signal paths                ; On                 ;      ;    ;
; Cut off clear and preset signal paths                 ; On                 ;      ;    ;
; Cut off feedback from I/O pins                        ; On                 ;      ;    ;
; Ignore Clock Settings                                 ; Off                ;      ;    ;
; Analyze latches as synchronous elements               ; Off                ;      ;    ;
+-------------------------------------------------------+--------------------+------+----+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Summary                                                                                                                                                                                                                                                                                                                                                    ;
+------------------------------+------------------------------------------+---------------+------------------------------------------------+-----------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------+------------+----------+--------------+
; Type                         ; Slack                                    ; Required Time ; Actual Time                                    ; From                                                                        ; To                                                                                                         ; From Clock ; To Clock ; Failed Paths ;
+------------------------------+------------------------------------------+---------------+------------------------------------------------+-----------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------+------------+----------+--------------+
; Worst-case tsu               ; N/A                                      ; None          ; 9.174 ns                                       ; CS                                                                          ; BUS_1:inst5|RAMTMP7[0]                                                                                     ;            ; CLK      ; 0            ;
; Worst-case tco               ; N/A                                      ; None          ; 12.419 ns                                      ; DA5180:inst3|DD[6]                                                          ; DAOUT[6]                                                                                                   ; CLK        ;          ; 0            ;
; Worst-case th                ; N/A                                      ; None          ; 2.726 ns                                       ; P0[6]                                                                       ; BUS_1:inst5|LATCH_ADDRES[6]                                                                                ;            ; ALE      ; 0            ;
; Worst-case Minimum tco       ; N/A                                      ; None          ; 6.500 ns                                       ; BUS_1:inst5|P0_OUT[6]                                                       ; P0[6]                                                                                                      ; CLK        ;          ; 0            ;
; Clock Setup: 'CLK'           ; N/A                                      ; None          ; 60.31 MHz ( period = 16.580 ns )               ; GET_RDADDR:inst10|COUNTER[9]                                                ; dram:inst14|altsyncram:altsyncram_component|altsyncram_3771:auto_generated|ram_block1a3~portb_address_reg9 ; CLK        ; CLK      ; 0            ;
; Clock Setup: 'CLK2'          ; N/A                                      ; None          ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; FREQ_COUNT:inst6|lpm_counter:COUNT2_rtl_0|cntr_e08:auto_generated|safe_q[0] ; FREQ_COUNT:inst6|lpm_counter:COUNT2_rtl_0|cntr_e08:auto_generated|safe_q[15]                               ; CLK2       ; CLK2     ; 0            ;
; Clock Hold: 'CLK'            ; Not operational: Clock Skew > Data Delay ; None          ; N/A                                            ; BUS_1:inst5|RAMTMP5[1]                                                      ; VOLTAGE_CONV:inst12|TEMP[1]                                                                                ; CLK        ; CLK      ; 235          ;
; Total number of failed paths ;                                          ;               ;                                                ;                                                                             ;                                                                                                            ;            ;          ; 235          ;
+------------------------------+------------------------------------------+---------------+------------------------------------------------+-----------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------+------------+----------+--------------+


+--------------------------------------------------------------------------------------------------------------------------------------+
; Clock Settings Summary                                                                                                               ;
+-----------------+--------------------+----------+------------------+----------+-----------------------+---------------------+--------+
; Clock Node Name ; Clock Setting Name ; Type     ; Fmax Requirement ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset ;