generator_add.vhd

数字示波器的FPGA实现 VHDL编写 Quartus7.1测试通过

------------------------------------------------------------------------------------
-- DESCRIPTION   :  cascadable Adder
--                  Width: 6
--
-- 
------------------------------------------------------------------------------------


library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_UNSIGNED.all;

entity generator_add is
	port (
        A : in std_logic_vector (7 downto 0);
	    B : in std_logic_vector (7 downto 0);
		Q : out std_logic_vector (7 downto 0)
		
	);
end entity;

--}} End of automatically maintained section

architecture add_anGen_arch of generator_add is
SIGNAL TEMP: STD_LOGIC_VECTOR (7 DOWNTO 0);
begin
	process (A ,B)
	begin
		TEMP <= A + B;
	end process;

    PROCESS(TEMP)
    BEGIN
        IF TEMP>="11001000" THEN
            Q<=TEMP - "11001000";
        ELSE Q<=TEMP;
        END IF;
    END PROCESS;

end architecture add_anGen_arch;