ampl_count.vhd

数字示波器的FPGA实现 VHDL编写 Quartus7.1测试通过

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
ENTITY AMPL_COUNT IS
PORT
   (
    CLKIN:IN STD_LOGIC;
    AIN: IN STD_LOGIC_VECTOR(7 DOWNTO 0);
    CLR: IN STD_LOGIC;
    Q:OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END;

ARCHITECTURE ART OF AMPL_COUNT IS

SIGNAL FULL:STD_LOGIC;
SIGNAL TEMP: STD_LOGIC_VECTOR(15 DOWNTO 0);
BEGIN 
    PROCESS(CLKIN,CLR)
    VARIABLE COUNT:INTEGER RANGE 0 TO 2048;
    VARIABLE MAX,MIN:STD_LOGIC_VECTOR(7 DOWNTO 0);
    BEGIN
    IF CLR='1' THEN
        COUNT:=0;
 --       FULL<='0';
        MAX:="00000000";
        MIN:="11111111";
   ELSIF CLKIN 'EVENT AND CLKIN='1' THEN 
       IF COUNT > 2000 THEN 
            COUNT:=2040;
            Q<=MAX - MIN;
       ELSE
            COUNT:=COUNT+1;
            IF MAX < AIN THEN 
                MAX:=AIN;
            END IF;
            IF MIN > AIN THEN
                MIN:=AIN;
            END IF;
       END IF;
    END IF;
    END PROCESS;

END;