sram_w.vhd

来自「数字示波器的FPGA实现 VHDL编写 Quartus7.1测试通过」· VHDL 代码 · 共 53 行

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;

ENTITY SRAM_W IS
PORT(
      CLK,EN: IN STD_LOGIC;
      DATASOUT: OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
      ADDOUT: OUT STD_LOGIC_VECTOR(13 DOWNTO 0);
      RDS1,WRS1,FINISH: OUT STD_LOGIC
);
END ;

ARCHITECTURE ART OF SRAM_W IS
begin

	process(clk, EN)
	variable data: std_logic_vector (7 downto 0);
    variable wr,mu: std_logic;
	variable cnt,CNT1 : integer range 0 to 5 ;
	variable cnt2 : integer range 0 to 255 ;
	begin
		if(clk'event and clk = '1') then 
			case cnt is
				when 0 => 
					WR := '1';
				when 1 =>
					IF EN='1' THEN
                        DATA:="00000000";
                        CNT2:=0;
                        FINISH<='0';
                    ELSIF CNT2=255 THEN
                        FINISH<='1';
                        CNT:=1;
                    ELSE CNT2:=CNT2+1;
                    END IF;
				when 3 =>
					WR := '0';
                    DATA:=CONV_STD_LOGIC_VECTOR(CNT2,8);
				when others =>
					CNT1:=CNT1+1;
			end case;
			cnt := cnt + 1;
		end if;
    WRS1<=WR;            
    ADDOUT<=CONV_STD_LOGIC_VECTOR(CNT2,14);
    DATASOUT<=DATA;
END PROCESS;
    RDS1<='1';
END ART;