maxplusii_to_quartus_name_mapping.txt

数字示波器的FPGA实现 VHDL编写 Quartus7.1测试通过

 -- Copyright (C) 1991-2004 Altera Corporation
 -- Any  megafunction  design,  and related netlist (encrypted  or  decrypted),
 -- support information,  device programming or simulation file,  and any other
 -- associated  documentation or information  provided by  Altera  or a partner
 -- under  Altera's   Megafunction   Partnership   Program  may  be  used  only
 -- to program  PLD  devices (but not masked  PLD  devices) from  Altera.   Any
 -- other  use  of such  megafunction  design,  netlist,  support  information,
 -- device programming or simulation file,  or any other  related documentation
 -- or information  is prohibited  for  any  other purpose,  including, but not
 -- limited to  modification,  reverse engineering,  de-compiling, or use  with
 -- any other  silicon devices,  unless such use is  explicitly  licensed under
 -- a separate agreement with  Altera  or a megafunction partner.  Title to the
 -- intellectual property,  including patents,  copyrights,  trademarks,  trade
 -- secrets,  or maskworks,  embodied in any such megafunction design, netlist,
 -- support  information,  device programming or simulation file,  or any other
 -- related documentation or information provided by  Altera  or a megafunction
 -- partner, remains with Altera, the megafunction partner, or their respective
 -- licensors. No other licenses, including any licenses needed under any third
 -- party's intellectual property, are provided herein.

 -- VERSION "Version 4.1 Build 181 06/29/2004 SJ Full Version"
 -- DATE "08/07/2005 20:27:24"

Conversion results for test_ad
+-----------------------+----------------------+
| MAX+PLUS II node name | Quartus II node name |
+-----------------------+----------------------+
| |A0                   | A[0]                 |
| |A1                   | A[1]                 |
| |ADIN0                | ADIN[0]              |
| |ADIN1                | ADIN[1]              |
| |ADIN2                | ADIN[2]              |
| |ADIN3                | ADIN[3]              |
| |ADIN4                | ADIN[4]              |
| |ADIN5                | ADIN[5]              |
| |ADIN6                | ADIN[6]              |
| |ADIN7                | ADIN[7]              |
| |CSDA1                | CSDA[1]              |
| |CSDA2                | CSDA[2]              |
| |DAOUT0               | DAOUT[0]             |
| |DAOUT1               | DAOUT[1]             |
| |DAOUT2               | DAOUT[2]             |
| |DAOUT3               | DAOUT[3]             |
| |DAOUT4               | DAOUT[4]             |
| |DAOUT5               | DAOUT[5]             |
| |DAOUT6               | DAOUT[6]             |
| |DAOUT7               | DAOUT[7]             |
| |DAXOUT0              | DAXOUT[0]            |
| |DAXOUT1              | DAXOUT[1]            |
| |DAXOUT2              | DAXOUT[2]            |
| |DAXOUT3              | DAXOUT[3]            |
| |DAXOUT4              | DAXOUT[4]            |
| |DAXOUT5              | DAXOUT[5]            |
| |DAXOUT6              | DAXOUT[6]            |
| |DAXOUT7              | DAXOUT[7]            |
+-----------------------+----------------------+