voltage_conv.vhd

来自「数字示波器的FPGA实现 VHDL编写 Quartus7.1测试通过」· VHDL 代码 · 共 49 行

------------------------------------------------------------------------------------
-- DESCRIPTION   :  Flip-flop D type
--                  Width: 8
--                  Clock active: high
--                  Asynchronous clear active: high
--                  Clock enable active: high
-- 
------------------------------------------------------------------------------------



library IEEE;
use IEEE.std_logic_1164.all;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;

entity VOLTAGE_CONV is
	port (
		ADEN,CLKK : in std_logic;
		DATA : in std_logic_vector (7 downto 0);
		POSY_A: IN STD_LOGIC_VECTOR( 7 DOWNTO 0);
		Q : out std_logic_vector (9 downto 0)
	);
end entity;



architecture ART of VOLTAGE_CONV is
signal TEMP: std_logic_vector (7 downto 0);
begin

	process (ADEN,CLKK,POSY_A)
	begin
    IF ADEN='0' THEN
          TEMP<="00000000";

	ELSE
		if FALLing_edge(CLKK) then
	           IF(DATA+POSY_A>=DATA)THEN 
	               TEMP<=DATA+POSY_A;
	            END IF;
		end if;
    END IF;
	end process;

	Q <= TEMP & "00";
          
end architecture;