sram_rw.vhd

数字示波器的FPGA实现 VHDL编写 Quartus7.1测试通过

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;

ENTITY SRAM_RW IS
PORT(
      CLK: IN STD_LOGIC;
      DATASIN: IN STD_LOGIC_VECTOR(7 DOWNTO 0);
      DATAMOUT: OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
      ADDRESSIN: IN STD_LOGIC_VECTOR(13 DOWNTO 0);
      ADDRESSOUT: OUT STD_LOGIC_VECTOR(13 DOWNTO 0);
      RD,CS,WR,READY: IN STD_LOGIC;
      RDS,WRS: OUT STD_LOGIC
);
END ;

ARCHITECTURE ART OF SRAM_RW IS
SIGNAL ADDRESS: STD_LOGIC_VECTOR(13 DOWNTO 0);
SIGNAL ADDRESS1: STD_LOGIC_VECTOR(13 DOWNTO 0);
SIGNAL RESET: STD_LOGIC;
BEGIN
DATAMOUT<=DATASIN;
ADDRESSOUT<=ADDRESS;
RDS<=RD;
WRS<='1';
PROCESS(WR,READY,CS)
BEGIN
IF WR'EVENT AND WR='1' THEN
  IF READY='1'AND CS='0' THEN
        ADDRESS1<=ADDRESSIN-1;
        RESET<='1';
  END IF;
END IF;
END PROCESS;
PROCESS(RD,READY,CS)
BEGIN
IF (RD'EVENT AND RD='0') THEN
    IF READY='1' AND CS='0' THEN
        IF RESET<='1' THEN 
           ADDRESS<=ADDRESS1;
           RESET<='0';
        ELSE 
           ADDRESS<=ADDRESS+1;
        END IF;
    END IF;
END IF;
END PROCESS;

--PROCESS(RD,CS)
--BEGIN
--IF RD'EVENT AND RD='0' THEN
--    IF CS='0' THEN
--
 --   END IF;
--END IF;
--END PROCESS;

END ART;