get_rdaddr.vhd

数字示波器的FPGA实现 VHDL编写 Quartus7.1测试通过

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
USE IEEE.STD_LOGIC_ARITH.ALL;

entity GET_RDADDR is
	port (
		CLK : in std_logic;
	    CLR : in std_logic;
	    PHASE: IN STD_LOGIC_VECTOR(10 DOWNTO 0);
		Q : out std_logic_vector (10 downto 0)
	);
end entity;

architecture ART of GET_RDADDR is

begin
	process(CLK,CLR,PHASE)
	VARIABLE COUNTER:INTEGER RANGE 0 TO 2048;  --引用常数N
	begin
      if CLR = '1' then
		COUNTER:=CONV_INTEGER(PHASE);
	  ELSIF CLK 'EVENT AND CLK='0' then 
         IF (COUNTER=2048 OR COUNTER=2047)THEN  
              COUNTER:=COUNTER;     
         --   COUNTER:=CONV_INTEGER(PHASE);
         ELSE
            COUNTER:=COUNTER+1;
         END IF;
      END IF;
    Q<=CONV_STD_LOGIC_VECTOR(COUNTER,11);

    END PROCESS;

end architecture;