scanwave.map.rpt

数字示波器的FPGA实现 VHDL编写 Quartus7.1测试通过

    Info: Found entity 1: generator_reg81
Info: Found 2 design units, including 1 entities, in source file GET_RDADDR.VHD
    Info: Found design unit 1: GET_RDADDR-ART
    Info: Found entity 1: GET_RDADDR
Info: Found 2 design units, including 1 entities, in source file max114.vhd
    Info: Found design unit 1: MAX114-BEHAV
    Info: Found entity 1: MAX114
Info: Found 2 design units, including 1 entities, in source file VOLTAGE_CONV.vhd
    Info: Found design unit 1: VOLTAGE_CONV-ART
    Info: Found entity 1: VOLTAGE_CONV
Info: Found 1 design units, including 1 entities, in source file SCANWAVE.bdf
    Info: Found entity 1: SCANWAVE
Info: Found 2 design units, including 1 entities, in source file fredevider2.vhd
    Info: Found design unit 1: FREDEVIDER2-ART
    Info: Found entity 1: FREDEVIDER2
Info: Found 2 design units, including 1 entities, in source file MUX2_3.vhd
    Info: Found design unit 1: MUX2_3-ART
    Info: Found entity 1: MUX2_3
Info: Found 2 design units, including 1 entities, in source file freq_count.vhd
    Info: Found design unit 1: FREQ_COUNT-ART
    Info: Found entity 1: FREQ_COUNT
Info: Found 2 design units, including 1 entities, in source file fredevider10.vhd
    Info: Found design unit 1: FREDEVIDER10-ART
    Info: Found entity 1: FREDEVIDER10
Info: Found 2 design units, including 1 entities, in source file AMPL_COUNT.vhd
    Info: Found design unit 1: AMPL_COUNT-ART
    Info: Found entity 1: AMPL_COUNT
Info: Found 1 design units, including 1 entities, in source file SCANWAVE_2.bdf
    Info: Found entity 1: SCANWAVE_2
Info: Found 1 design units, including 1 entities, in source file SCANWAVE_3.bdf
    Info: Found entity 1: SCANWAVE_3
Info: Elaborating entity "SCANWAVE" for the top level hierarchy
Info: Elaborating entity "MAX114" for hierarchy "MAX114:inst11"
Info: Elaborating entity "generator_reg81" for hierarchy "generator_reg81:79"
Info: Elaborating entity "BUS_1" for hierarchy "BUS_1:inst5"
Warning (10036): Verilog HDL or VHDL warning at BUS_1.vhd(24): object "RAMTMP3" assigned a value but never read
Warning (10036): Verilog HDL or VHDL warning at BUS_1.vhd(25): object "RAMTMP4" assigned a value but never read
Warning (10036): Verilog HDL or VHDL warning at BUS_1.vhd(28): object "RAMTMP" assigned a value but never read
Info: Elaborating entity "AMPL_COUNT" for hierarchy "AMPL_COUNT:inst2"
Info: Elaborating entity "FREDEVIDER2" for hierarchy "FREDEVIDER2:inst13"
Warning: Using design file dram.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project
    Info: Found design unit 1: dram-SYN
    Info: Found entity 1: dram
Info: Elaborating entity "dram" for hierarchy "dram:inst"
Info: Found 1 design units, including 1 entities, in source file c:/altera/71/quartus/libraries/megafunctions/altsyncram.tdf
    Info: Found entity 1: altsyncram
Info: Elaborating entity "altsyncram" for hierarchy "dram:inst|altsyncram:altsyncram_component"
Info: Elaborated megafunction instantiation "dram:inst|altsyncram:altsyncram_component"
Info: Found 1 design units, including 1 entities, in source file db/altsyncram_fbg1.tdf
    Info: Found entity 1: altsyncram_fbg1
Info: Elaborating entity "altsyncram_fbg1" for hierarchy "dram:inst|altsyncram:altsyncram_component|altsyncram_fbg1:auto_generated"
Info: Elaborating entity "AD_SRAM" for hierarchy "AD_SRAM:inst19"
Info: Elaborating entity "CONV_SINGLE" for hierarchy "CONV_SINGLE:inst22"
Warning (10492): VHDL Process Statement warning at CONV_SINGLE.vhd(24): signal "CURRENT_STATE" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning (10631): VHDL Process Statement warning at CONV_SINGLE.vhd(22): inferring latch(es) for signal or variable "TEMP", which holds its previous value in one or more paths through the process
Info (10041): Inferred latch for "TEMP[0]" at CONV_SINGLE.vhd(22)
Info (10041): Inferred latch for "TEMP[1]" at CONV_SINGLE.vhd(22)
Info (10041): Inferred latch for "TEMP[2]" at CONV_SINGLE.vhd(22)
Info (10041): Inferred latch for "TEMP[3]" at CONV_SINGLE.vhd(22)
Info (10041): Inferred latch for "TEMP[4]" at CONV_SINGLE.vhd(22)
Info (10041): Inferred latch for "TEMP[5]" at CONV_SINGLE.vhd(22)
Info (10041): Inferred latch for "TEMP[6]" at CONV_SINGLE.vhd(22)
Info (10041): Inferred latch for "TEMP[7]" at CONV_SINGLE.vhd(22)
Info: Elaborating entity "GET_RDADDR" for hierarchy "GET_RDADDR:inst10"
Info: Elaborating entity "generator_accB" for hierarchy "generator_accB:inst4"
Info: Elaborating entity "FREDEVIDER8" for hierarchy "FREDEVIDER8:inst8"
Info: Elaborating entity "bustri" for hierarchy "bustri:inst1"
Info: Found 1 design units, including 1 entities, in source file c:/altera/71/quartus/libraries/megafunctions/lpm_bustri.tdf
    Info: Found entity 1: lpm_bustri
Info: Elaborating entity "lpm_bustri" for hierarchy "bustri:inst1|lpm_bustri:lpm_bustri_component"
Info: Elaborated megafunction instantiation "bustri:inst1|lpm_bustri:lpm_bustri_component"
Info: Elaborating entity "FREQ_COUNT" for hierarchy "FREQ_COUNT:inst6"
Info: Elaborating entity "FREDEVIDER10" for hierarchy "FREDEVIDER10:inst18"
Info: Elaborating entity "MUX2_3" for hierarchy "MUX2_3:inst3"
Info: Elaborating entity "VOLTAGE_CONV" for hierarchy "VOLTAGE_CONV:inst17"
Info: Elaborating entity "MUX2_1" for hierarchy "MUX2_1:inst32"
Warning: Converted TRI buffer or tri-state bus to logic, or removed OPNDRN
    Warning: Converting TRI node "bustri:inst1|lpm_bustri:lpm_bustri_component|din[7]" that feeds logic to a wire
    Warning: Converting TRI node "bustri:inst1|lpm_bustri:lpm_bustri_component|din[6]" that feeds logic to a wire
    Warning: Converting TRI node "bustri:inst1|lpm_bustri:lpm_bustri_component|din[5]" that feeds logic to a wire
    Warning: Converting TRI node "bustri:inst1|lpm_bustri:lpm_bustri_component|din[4]" that feeds logic to a wire
    Warning: Converting TRI node "bustri:inst1|lpm_bustri:lpm_bustri_component|din[3]" that feeds logic to a wire
    Warning: Converting TRI node "bustri:inst1|lpm_bustri:lpm_bustri_component|din[2]" that feeds logic to a wire
    Warning: Converting TRI node "bustri:inst1|lpm_bustri:lpm_bustri_component|din[1]" that feeds logic to a wire
    Warning: Converting TRI node "bustri:inst1|lpm_bustri:lpm_bustri_component|din[0]" that feeds logic to a wire
Info: State machine "|SCANWAVE|CONV_SINGLE:inst22|CURRENT_STATE" contains 5 states
Info: Selected Auto state machine encoding method for state machine "|SCANWAVE|CONV_SINGLE:inst22|CURRENT_STATE"
Info: Encoding result for state machine "|SCANWAVE|CONV_SINGLE:inst22|CURRENT_STATE"
    Info: Completed encoding using 5 state bits
        Info: Encoded state bit "CONV_SINGLE:inst22|CURRENT_STATE.st4"
        Info: Encoded state bit "CONV_SINGLE:inst22|CURRENT_STATE.st3"
        Info: Encoded state bit "CONV_SINGLE:inst22|CURRENT_STATE.st2"
        Info: Encoded state bit "CONV_SINGLE:inst22|CURRENT_STATE.st1"
        Info: Encoded state bit "CONV_SINGLE:inst22|CURRENT_STATE.st0"
    Info: State "|SCANWAVE|CONV_SINGLE:inst22|CURRENT_STATE.st0" uses code string "00000"
    Info: State "|SCANWAVE|CONV_SINGLE:inst22|CURRENT_STATE.st1" uses code string "00011"
    Info: State "|SCANWAVE|CONV_SINGLE:inst22|CURRENT_STATE.st2" uses code string "00101"
    Info: State "|SCANWAVE|CONV_SINGLE:inst22|CURRENT_STATE.st3" uses code string "01001"
    Info: State "|SCANWAVE|CONV_SINGLE:inst22|CURRENT_STATE.st4" uses code string "10001"
Info: Duplicate registers merged to single register
    Info: Duplicate register "FREDEVIDER10:inst18|COUNTER[0]" merged to single register "FREDEVIDER8:inst8|COUNTER[0]"
Warning: Output pins are stuck at VCC or GND
    Warning: Pin "A1" stuck at GND
    Warning: Pin "A0" stuck at GND
    Warning: Pin "CSDA2" stuck at GND
    Warning: Pin "XFER" stuck at GND
    Warning: Pin "CSDA1" stuck at GND
    Warning: Pin "WRDA" stuck at GND
Info: Registers with preset signals will power-up high
Info: 1 registers lost all their fanouts during netlist optimizations. The first 1 are displayed below.
    Info: Register "inst6/COUNT2[16]" lost all its fanouts during netlist optimizations.
Warning: Design contains 5 input pin(s) that do not drive logic
    Warning: No output dependent on input pin "P2[4]"
    Warning: No output dependent on input pin "P2[3]"
    Warning: No output dependent on input pin "P2[2]"
    Warning: No output dependent on input pin "P2[1]"
    Warning: No output dependent on input pin "P2[0]"
Info: Implemented 587 device resources after synthesis - the final resource count might be different
    Info: Implemented 20 input pins
    Info: Implemented 25 output pins
    Info: Implemented 8 bidirectional pins
    Info: Implemented 518 logic cells
    Info: Implemented 16 RAM segments
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 28 warnings
    Info: Allocated 162 megabytes of memory during processing
    Info: Processing ended: Tue Aug 28 09:56:26 2007
    Info: Elapsed time: 00:00:10