📄 scanwave.map.rpt
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; RDCONTROL_ACLR_B ; NONE ; Untyped ;
; BYTEENA_ACLR_B ; NONE ; Untyped ;
; WIDTH_BYTEENA_A ; 1 ; Signed Integer ;
; WIDTH_BYTEENA_B ; 1 ; Untyped ;
; RAM_BLOCK_TYPE ; M4K ; Untyped ;
; BYTE_SIZE ; 8 ; Untyped ;
; READ_DURING_WRITE_MODE_MIXED_PORTS ; DONT_CARE ; Untyped ;
; READ_DURING_WRITE_MODE_PORT_A ; NEW_DATA_NO_NBE_READ ; Untyped ;
; READ_DURING_WRITE_MODE_PORT_B ; NEW_DATA_NO_NBE_READ ; Untyped ;
; INIT_FILE ; UNUSED ; Untyped ;
; INIT_FILE_LAYOUT ; PORT_A ; Untyped ;
; MAXIMUM_DEPTH ; 0 ; Untyped ;
; CLOCK_ENABLE_INPUT_A ; NORMAL ; Untyped ;
; CLOCK_ENABLE_INPUT_B ; NORMAL ; Untyped ;
; CLOCK_ENABLE_OUTPUT_A ; NORMAL ; Untyped ;
; CLOCK_ENABLE_OUTPUT_B ; NORMAL ; Untyped ;
; CLOCK_ENABLE_CORE_A ; USE_INPUT_CLKEN ; Untyped ;
; CLOCK_ENABLE_CORE_B ; USE_INPUT_CLKEN ; Untyped ;
; ENABLE_ECC ; FALSE ; Untyped ;
; DEVICE_FAMILY ; Cyclone ; Untyped ;
; CBXI_PARAMETER ; altsyncram_fbg1 ; Untyped ;
+------------------------------------+----------------------+----------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+-------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: bustri:inst1|lpm_bustri:lpm_bustri_component ;
+----------------+-------+------------------------------------------------------------------+
; Parameter Name ; Value ; Type ;
+----------------+-------+------------------------------------------------------------------+
; LPM_WIDTH ; 8 ; Signed Integer ;
+----------------+-------+------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: dram:inst14|altsyncram:altsyncram_component ;
+------------------------------------+----------------------+------------------------------+
; Parameter Name ; Value ; Type ;
+------------------------------------+----------------------+------------------------------+
; BYTE_SIZE_BLOCK ; 8 ; Untyped ;
; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ;
; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ;
; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ;
; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ;
; WIDTH_BYTEENA ; 1 ; Untyped ;
; OPERATION_MODE ; DUAL_PORT ; Untyped ;
; WIDTH_A ; 8 ; Signed Integer ;
; WIDTHAD_A ; 11 ; Signed Integer ;
; NUMWORDS_A ; 2048 ; Signed Integer ;
; OUTDATA_REG_A ; UNREGISTERED ; Untyped ;
; ADDRESS_ACLR_A ; NONE ; Untyped ;
; OUTDATA_ACLR_A ; NONE ; Untyped ;
; WRCONTROL_ACLR_A ; NONE ; Untyped ;
; INDATA_ACLR_A ; NONE ; Untyped ;
; BYTEENA_ACLR_A ; NONE ; Untyped ;
; WIDTH_B ; 8 ; Signed Integer ;
; WIDTHAD_B ; 11 ; Signed Integer ;
; NUMWORDS_B ; 2048 ; Signed Integer ;
; INDATA_REG_B ; CLOCK1 ; Untyped ;
; WRCONTROL_WRADDRESS_REG_B ; CLOCK1 ; Untyped ;
; RDCONTROL_REG_B ; CLOCK1 ; Untyped ;
; ADDRESS_REG_B ; CLOCK1 ; Untyped ;
; OUTDATA_REG_B ; UNREGISTERED ; Untyped ;
; BYTEENA_REG_B ; CLOCK1 ; Untyped ;
; INDATA_ACLR_B ; NONE ; Untyped ;
; WRCONTROL_ACLR_B ; NONE ; Untyped ;
; ADDRESS_ACLR_B ; NONE ; Untyped ;
; OUTDATA_ACLR_B ; NONE ; Untyped ;
; RDCONTROL_ACLR_B ; NONE ; Untyped ;
; BYTEENA_ACLR_B ; NONE ; Untyped ;
; WIDTH_BYTEENA_A ; 1 ; Signed Integer ;
; WIDTH_BYTEENA_B ; 1 ; Untyped ;
; RAM_BLOCK_TYPE ; M4K ; Untyped ;
; BYTE_SIZE ; 8 ; Untyped ;
; READ_DURING_WRITE_MODE_MIXED_PORTS ; DONT_CARE ; Untyped ;
; READ_DURING_WRITE_MODE_PORT_A ; NEW_DATA_NO_NBE_READ ; Untyped ;
; READ_DURING_WRITE_MODE_PORT_B ; NEW_DATA_NO_NBE_READ ; Untyped ;
; INIT_FILE ; UNUSED ; Untyped ;
; INIT_FILE_LAYOUT ; PORT_A ; Untyped ;
; MAXIMUM_DEPTH ; 0 ; Untyped ;
; CLOCK_ENABLE_INPUT_A ; NORMAL ; Untyped ;
; CLOCK_ENABLE_INPUT_B ; NORMAL ; Untyped ;
; CLOCK_ENABLE_OUTPUT_A ; NORMAL ; Untyped ;
; CLOCK_ENABLE_OUTPUT_B ; NORMAL ; Untyped ;
; CLOCK_ENABLE_CORE_A ; USE_INPUT_CLKEN ; Untyped ;
; CLOCK_ENABLE_CORE_B ; USE_INPUT_CLKEN ; Untyped ;
; ENABLE_ECC ; FALSE ; Untyped ;
; DEVICE_FAMILY ; Cyclone ; Untyped ;
; CBXI_PARAMETER ; altsyncram_fbg1 ; Untyped ;
+------------------------------------+----------------------+------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
Info: Version 7.1 Build 156 04/30/2007 SJ Web Edition
Info: Processing started: Tue Aug 28 09:56:16 2007
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off scanwave -c scanwave
Info: Found 2 design units, including 1 entities, in source file MUX2_1.vhd
Info: Found design unit 1: MUX2_1-ART
Info: Found entity 1: MUX2_1
Info: Found 2 design units, including 1 entities, in source file AD_SRAM.vhd
Info: Found design unit 1: AD_SRAM-ART
Info: Found entity 1: AD_SRAM
Info: Found 2 design units, including 1 entities, in source file BUS_1.vhd
Info: Found design unit 1: BUS_1-ART
Info: Found entity 1: BUS_1
Info: Found 2 design units, including 1 entities, in source file BUSTRI.vhd
Info: Found design unit 1: bustri-SYN
Info: Found entity 1: bustri
Info: Found 2 design units, including 1 entities, in source file CONV_SINGLE.vhd
Info: Found design unit 1: CONV_SINGLE-ART
Info: Found entity 1: CONV_SINGLE
Info: Found 2 design units, including 1 entities, in source file fredevider8.vhd
Info: Found design unit 1: FREDEVIDER8-ART
Info: Found entity 1: FREDEVIDER8
Info: Found 2 design units, including 1 entities, in source file generator_accb.vhd
Info: Found design unit 1: generator_accB-acc_arch
Info: Found entity 1: generator_accB
Info: Found 2 design units, including 1 entities, in source file GENERATOR_ADD.vhd
Info: Found design unit 1: generator_add-add_anGen_arch
Info: Found entity 1: generator_add
Info: Found 2 design units, including 1 entities, in source file generator_reg8.vhd
Info: Found design unit 1: generator_reg8-reg_arch8
Info: Found entity 1: generator_reg8
Info: Found 2 design units, including 1 entities, in source file generator_reg81.vhd
Info: Found design unit 1: generator_reg81-reg_arch8
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