📄 scanwave.map.rpt
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+----------------------------------------------------+--------------------------------------+------------------------+
; CONV_SINGLE:inst22|TEMP[7] ; CONV_SINGLE:inst22|CURRENT_STATE.st1 ; yes ;
; CONV_SINGLE:inst22|TEMP[6] ; CONV_SINGLE:inst22|CURRENT_STATE.st1 ; yes ;
; CONV_SINGLE:inst22|TEMP[5] ; CONV_SINGLE:inst22|CURRENT_STATE.st1 ; yes ;
; CONV_SINGLE:inst22|TEMP[4] ; CONV_SINGLE:inst22|CURRENT_STATE.st1 ; yes ;
; CONV_SINGLE:inst22|TEMP[3] ; CONV_SINGLE:inst22|CURRENT_STATE.st1 ; yes ;
; CONV_SINGLE:inst22|TEMP[2] ; CONV_SINGLE:inst22|CURRENT_STATE.st1 ; yes ;
; CONV_SINGLE:inst22|TEMP[1] ; CONV_SINGLE:inst22|CURRENT_STATE.st1 ; yes ;
; CONV_SINGLE:inst22|TEMP[0] ; CONV_SINGLE:inst22|CURRENT_STATE.st1 ; yes ;
; Number of user-specified and inferred latches = 8 ; ; ;
+----------------------------------------------------+--------------------------------------+------------------------+
Note: All latches listed above may not be present at the end of synthesis due to various synthesis optimizations.
+----------------------------------------------------------------------+
; Registers Removed During Synthesis ;
+---------------------------------------+------------------------------+
; Register name ; Reason for Removal ;
+---------------------------------------+------------------------------+
; inst18/COUNTER[0] ; Merged with inst8/COUNTER[0] ;
; inst6/COUNT2[16] ; Lost fanout ;
; Total Number of Removed Registers = 2 ; ;
+---------------------------------------+------------------------------+
+------------------------------------------------------+
; General Register Statistics ;
+----------------------------------------------+-------+
; Statistic ; Value ;
+----------------------------------------------+-------+
; Total registers ; 300 ;
; Number of registers using Synchronous Clear ; 0 ;
; Number of registers using Synchronous Load ; 36 ;
; Number of registers using Asynchronous Clear ; 137 ;
; Number of registers using Asynchronous Load ; 12 ;
; Number of registers using Clock Enable ; 193 ;
; Number of registers using Preset ; 0 ;
+----------------------------------------------+-------+
+--------------------------------------------------+
; Inverted Register Statistics ;
+----------------------------------------+---------+
; Inverted Register ; Fan out ;
+----------------------------------------+---------+
; AMPL_COUNT:inst2|MIN[7] ; 2 ;
; AMPL_COUNT:inst2|MIN[6] ; 2 ;
; AMPL_COUNT:inst2|MIN[5] ; 2 ;
; AMPL_COUNT:inst2|MIN[4] ; 2 ;
; AMPL_COUNT:inst2|MIN[3] ; 2 ;
; AMPL_COUNT:inst2|MIN[2] ; 2 ;
; AMPL_COUNT:inst2|MIN[1] ; 2 ;
; AMPL_COUNT:inst2|MIN[0] ; 2 ;
; Total number of inverted registers = 8 ; ;
+----------------------------------------+---------+
+-------------------------------------------------------------------------------------------------------------------------------------------------+
; Multiplexer Restructuring Statistics (Restructuring Performed) ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+-----------------------------------+
; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+-----------------------------------+
; 4:1 ; 12 bits ; 24 LEs ; 12 LEs ; 12 LEs ; Yes ; |SCANWAVE|AD_SRAM:inst20|cnt2[0] ;
; 4:1 ; 12 bits ; 24 LEs ; 12 LEs ; 12 LEs ; Yes ; |SCANWAVE|AD_SRAM:inst19|cnt2[3] ;
; 129:1 ; 8 bits ; 688 LEs ; 8 LEs ; 680 LEs ; Yes ; |SCANWAVE|BUS_1:inst5|RAMTMP11[2] ;
; 130:1 ; 2 bits ; 172 LEs ; 2 LEs ; 170 LEs ; Yes ; |SCANWAVE|BUS_1:inst5|RAMTMP0[0] ;
; 130:1 ; 8 bits ; 688 LEs ; 8 LEs ; 680 LEs ; Yes ; |SCANWAVE|BUS_1:inst5|RAMTMP2[6] ;
; 130:1 ; 8 bits ; 688 LEs ; 8 LEs ; 680 LEs ; Yes ; |SCANWAVE|BUS_1:inst5|RAMTMP10[6] ;
; 130:1 ; 8 bits ; 688 LEs ; 8 LEs ; 680 LEs ; Yes ; |SCANWAVE|BUS_1:inst5|RAMTMP5[2] ;
; 130:1 ; 8 bits ; 688 LEs ; 8 LEs ; 680 LEs ; Yes ; |SCANWAVE|BUS_1:inst5|RAMTMP7[1] ;
; 130:1 ; 8 bits ; 688 LEs ; 8 LEs ; 680 LEs ; Yes ; |SCANWAVE|BUS_1:inst5|RAMTMP9[5] ;
; 4:1 ; 8 bits ; 16 LEs ; 16 LEs ; 0 LEs ; Yes ; |SCANWAVE|BUS_1:inst5|P0_OUT[0] ;
; 5:1 ; 8 bits ; 24 LEs ; 16 LEs ; 8 LEs ; No ; |SCANWAVE|MUX2_3:inst3|Mux3 ;
; 10:1 ; 3 bits ; 18 LEs ; 18 LEs ; 0 LEs ; No ; |SCANWAVE|MAX114:inst11|Mux3 ;
; 11:1 ; 3 bits ; 21 LEs ; 15 LEs ; 6 LEs ; No ; |SCANWAVE|AD_SRAM:inst20|Mux2 ;
; 11:1 ; 3 bits ; 21 LEs ; 15 LEs ; 6 LEs ; No ; |SCANWAVE|AD_SRAM:inst19|Mux1 ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+-----------------------------------+
+-------------------------------------------------------------------------------------------------+
; Source assignments for dram:inst|altsyncram:altsyncram_component|altsyncram_fbg1:auto_generated ;
+---------------------------------+--------------------+------+-----------------------------------+
; Assignment ; Value ; From ; To ;
+---------------------------------+--------------------+------+-----------------------------------+
; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; - ; - ;
+---------------------------------+--------------------+------+-----------------------------------+
+---------------------------------------------------------------------------------------------------+
; Source assignments for dram:inst14|altsyncram:altsyncram_component|altsyncram_fbg1:auto_generated ;
+---------------------------------+--------------------+------+-------------------------------------+
; Assignment ; Value ; From ; To ;
+---------------------------------+--------------------+------+-------------------------------------+
; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; - ; - ;
+---------------------------------+--------------------+------+-------------------------------------+
+----------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: dram:inst|altsyncram:altsyncram_component ;
+------------------------------------+----------------------+----------------------------+
; Parameter Name ; Value ; Type ;
+------------------------------------+----------------------+----------------------------+
; BYTE_SIZE_BLOCK ; 8 ; Untyped ;
; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ;
; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ;
; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ;
; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ;
; WIDTH_BYTEENA ; 1 ; Untyped ;
; OPERATION_MODE ; DUAL_PORT ; Untyped ;
; WIDTH_A ; 8 ; Signed Integer ;
; WIDTHAD_A ; 11 ; Signed Integer ;
; NUMWORDS_A ; 2048 ; Signed Integer ;
; OUTDATA_REG_A ; UNREGISTERED ; Untyped ;
; ADDRESS_ACLR_A ; NONE ; Untyped ;
; OUTDATA_ACLR_A ; NONE ; Untyped ;
; WRCONTROL_ACLR_A ; NONE ; Untyped ;
; INDATA_ACLR_A ; NONE ; Untyped ;
; BYTEENA_ACLR_A ; NONE ; Untyped ;
; WIDTH_B ; 8 ; Signed Integer ;
; WIDTHAD_B ; 11 ; Signed Integer ;
; NUMWORDS_B ; 2048 ; Signed Integer ;
; INDATA_REG_B ; CLOCK1 ; Untyped ;
; WRCONTROL_WRADDRESS_REG_B ; CLOCK1 ; Untyped ;
; RDCONTROL_REG_B ; CLOCK1 ; Untyped ;
; ADDRESS_REG_B ; CLOCK1 ; Untyped ;
; OUTDATA_REG_B ; UNREGISTERED ; Untyped ;
; BYTEENA_REG_B ; CLOCK1 ; Untyped ;
; INDATA_ACLR_B ; NONE ; Untyped ;
; WRCONTROL_ACLR_B ; NONE ; Untyped ;
; ADDRESS_ACLR_B ; NONE ; Untyped ;
; OUTDATA_ACLR_B ; NONE ; Untyped ;
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