max114.vhd

数字示波器的FPGA实现 VHDL编写 Quartus7.1测试通过

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY MAX114 IS
    PORT (ADIN: IN STD_LOGIC_VECTOR(7 DOWNTO 0);
          CLK,INTN: IN STD_LOGIC;
          RDAD,CSAD: OUT STD_LOGIC;
          ADOUT_A,ADOUT_B: OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
          A0,A1,A: OUT STD_LOGIC );
END MAX114;

ARCHITECTURE BEHAV OF MAX114 IS

BEGIN
A0<='0';
A1<='0';
PROCESS(CLK,INTN,ADIN)
    VARIABLE  RD: STD_LOGIC;
    VARIABLE  B: STD_LOGIC;
	variable cnt : integer range 0 to 15 := 0;
BEGIN
IF CLK 'EVENT AND CLK='1' THEN
    CASE CNT IS
    WHEN 0=>
        RD:='1';
    WHEN 1=>
        IF(INTN='0') THEN
            CNT:=0;
        END IF;
    WHEN 2=>
        RD:='0'; 
           B:='0';
        IF(INTN='1') THEN
            CNT:=1;
        END IF;
    WHEN 7=>
        ADOUT_B<=ADIN;
    WHEN 8=>
        RD:='1';
    WHEN 9=>
        IF(INTN='0') THEN
            CNT:=8;
        END IF;
    WHEN 10=>
        RD:='0'; 
           B:='1';
        IF(INTN='1') THEN
            CNT:=9;
        END IF;
    WHEN 15=>
            ADOUT_A<=ADIN;
    WHEN OTHERS=>
        NULL;
    END CASE;
    CNT :=CNT + 1;
END IF;
RDAD<=RD;
CSAD<=RD;
A<=B;
END PROCESS;

END BEHAV;