scanwave.map.qmsg

数字示波器的FPGA实现 VHDL编写 Quartus7.1测试通过

{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "generator_reg81 generator_reg81:79 " "Info: Elaborating entity \"generator_reg81\" for hierarchy \"generator_reg81:79\"" {  } { { "SCANWAVE.bdf" "79" { Schematic "I:/数字存储示波器/scanwave/SCANWAVE.bdf" { { 784 760 952 864 "79" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "BUS_1 BUS_1:inst5 " "Info: Elaborating entity \"BUS_1\" for hierarchy \"BUS_1:inst5\"" {  } { { "SCANWAVE.bdf" "inst5" { Schematic "I:/数字存储示波器/scanwave/SCANWAVE.bdf" { { 720 232 408 976 "inst5" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "RAMTMP3 BUS_1.vhd(24) " "Warning (10036): Verilog HDL or VHDL warning at BUS_1.vhd(24): object \"RAMTMP3\" assigned a value but never read" {  } { { "BUS_1.vhd" "" { Text "I:/数字存储示波器/scanwave/BUS_1.vhd" 24 0 0 } }  } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0 "" 0}
{ "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "RAMTMP4 BUS_1.vhd(25) " "Warning (10036): Verilog HDL or VHDL warning at BUS_1.vhd(25): object \"RAMTMP4\" assigned a value but never read" {  } { { "BUS_1.vhd" "" { Text "I:/数字存储示波器/scanwave/BUS_1.vhd" 25 0 0 } }  } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0 "" 0}
{ "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "RAMTMP BUS_1.vhd(28) " "Warning (10036): Verilog HDL or VHDL warning at BUS_1.vhd(28): object \"RAMTMP\" assigned a value but never read" {  } { { "BUS_1.vhd" "" { Text "I:/数字存储示波器/scanwave/BUS_1.vhd" 28 0 0 } }  } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "AMPL_COUNT AMPL_COUNT:inst2 " "Info: Elaborating entity \"AMPL_COUNT\" for hierarchy \"AMPL_COUNT:inst2\"" {  } { { "SCANWAVE.bdf" "inst2" { Schematic "I:/数字存储示波器/scanwave/SCANWAVE.bdf" { { 472 1440 1576 568 "inst2" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "FREDEVIDER2 FREDEVIDER2:inst13 " "Info: Elaborating entity \"FREDEVIDER2\" for hierarchy \"FREDEVIDER2:inst13\"" {  } { { "SCANWAVE.bdf" "inst13" { Schematic "I:/数字存储示波器/scanwave/SCANWAVE.bdf" { { 168 696 824 264 "inst13" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Warning" "WSGN_SEARCH_FILE" "dram.vhd 2 1 " "Warning: Using design file dram.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 dram-SYN " "Info: Found design unit 1: dram-SYN" {  } { { "dram.vhd" "" { Text "I:/数字存储示波器/scanwave/dram.vhd" 59 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "1 dram " "Info: Found entity 1: dram" {  } { { "dram.vhd" "" { Text "I:/数字存储示波器/scanwave/dram.vhd" 45 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!d! design units and %3!d! entities in project" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "dram dram:inst " "Info: Elaborating entity \"dram\" for hierarchy \"dram:inst\"" {  } { { "SCANWAVE.bdf" "inst" { Schematic "I:/数字存储示波器/scanwave/SCANWAVE.bdf" { { 296 1104 1360 456 "inst" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "c:/altera/71/quartus/libraries/megafunctions/altsyncram.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file c:/altera/71/quartus/libraries/megafunctions/altsyncram.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram " "Info: Found entity 1: altsyncram" {  } { { "altsyncram.tdf" "" { Text "c:/altera/71/quartus/libraries/megafunctions/altsyncram.tdf" 435 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram dram:inst\|altsyncram:altsyncram_component " "Info: Elaborating entity \"altsyncram\" for hierarchy \"dram:inst\|altsyncram:altsyncram_component\"" {  } { { "dram.vhd" "altsyncram_component" { Text "I:/数字存储示波器/scanwave/dram.vhd" 100 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_ELABORATION_HEADER" "dram:inst\|altsyncram:altsyncram_component " "Info: Elaborated megafunction instantiation \"dram:inst\|altsyncram:altsyncram_component\"" {  } { { "dram.vhd" "" { Text "I:/数字存储示波器/scanwave/dram.vhd" 100 0 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_fbg1.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/altsyncram_fbg1.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_fbg1 " "Info: Found entity 1: altsyncram_fbg1" {  } { { "db/altsyncram_fbg1.tdf" "" { Text "I:/数字存储示波器/scanwave/db/altsyncram_fbg1.tdf" 36 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram_fbg1 dram:inst\|altsyncram:altsyncram_component\|altsyncram_fbg1:auto_generated " "Info: Elaborating entity \"altsyncram_fbg1\" for hierarchy \"dram:inst\|altsyncram:altsyncram_component\|altsyncram_fbg1:auto_generated\"" {  } { { "altsyncram.tdf" "auto_generated" { Text "c:/altera/71/quartus/libraries/megafunctions/altsyncram.tdf" 918 4 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "AD_SRAM AD_SRAM:inst19 " "Info: Elaborating entity \"AD_SRAM\" for hierarchy \"AD_SRAM:inst19\"" {  } { { "SCANWAVE.bdf" "inst19" { Schematic "I:/数字存储示波器/scanwave/SCANWAVE.bdf" { { 280 648 832 408 "inst19" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "CONV_SINGLE CONV_SINGLE:inst22 " "Info: Elaborating entity \"CONV_SINGLE\" for hierarchy \"CONV_SINGLE:inst22\"" {  } { { "SCANWAVE.bdf" "inst22" { Schematic "I:/数字存储示波器/scanwave/SCANWAVE.bdf" { { 560 536 736 688 "inst22" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "CURRENT_STATE CONV_SINGLE.vhd(24) " "Warning (10492): VHDL Process Statement warning at CONV_SINGLE.vhd(24): signal \"CURRENT_STATE\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" {  } { { "CONV_SINGLE.vhd" "" { Text "I:/数字存储示波器/scanwave/CONV_SINGLE.vhd" 24 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VHDL_ID_IN_COMB_PROCESS_HOLDS_VALUE" "TEMP CONV_SINGLE.vhd(22) " "Warning (10631): VHDL Process Statement warning at CONV_SINGLE.vhd(22): inferring latch(es) for signal or variable \"TEMP\", which holds its previous value in one or more paths through the process" {  } { { "CONV_SINGLE.vhd" "" { Text "I:/数字存储示波器/scanwave/CONV_SINGLE.vhd" 22 0 0 } }  } 0 10631 "VHDL Process Statement warning at %2!s!: inferring latch(es) for signal or variable \"%1!s!\", which holds its previous value in one or more paths through the process" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "TEMP\[0\] CONV_SINGLE.vhd(22) " "Info (10041): Inferred latch for \"TEMP\[0\]\" at CONV_SINGLE.vhd(22)" {  } { { "CONV_SINGLE.vhd" "" { Text "I:/数字存储示波器/scanwave/CONV_SINGLE.vhd" 22 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "TEMP\[1\] CONV_SINGLE.vhd(22) " "Info (10041): Inferred latch for \"TEMP\[1\]\" at CONV_SINGLE.vhd(22)" {  } { { "CONV_SINGLE.vhd" "" { Text "I:/数字存储示波器/scanwave/CONV_SINGLE.vhd" 22 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "TEMP\[2\] CONV_SINGLE.vhd(22) " "Info (10041): Inferred latch for \"TEMP\[2\]\" at CONV_SINGLE.vhd(22)" {  } { { "CONV_SINGLE.vhd" "" { Text "I:/数字存储示波器/scanwave/CONV_SINGLE.vhd" 22 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "TEMP\[3\] CONV_SINGLE.vhd(22) " "Info (10041): Inferred latch for \"TEMP\[3\]\" at CONV_SINGLE.vhd(22)" {  } { { "CONV_SINGLE.vhd" "" { Text "I:/数字存储示波器/scanwave/CONV_SINGLE.vhd" 22 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "TEMP\[4\] CONV_SINGLE.vhd(22) " "Info (10041): Inferred latch for \"TEMP\[4\]\" at CONV_SINGLE.vhd(22)" {  } { { "CONV_SINGLE.vhd" "" { Text "I:/数字存储示波器/scanwave/CONV_SINGLE.vhd" 22 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "TEMP\[5\] CONV_SINGLE.vhd(22) " "Info (10041): Inferred latch for \"TEMP\[5\]\" at CONV_SINGLE.vhd(22)" {  } { { "CONV_SINGLE.vhd" "" { Text "I:/数字存储示波器/scanwave/CONV_SINGLE.vhd" 22 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "TEMP\[6\] CONV_SINGLE.vhd(22) " "Info (10041): Inferred latch for \"TEMP\[6\]\" at CONV_SINGLE.vhd(22)" {  } { { "CONV_SINGLE.vhd" "" { Text "I:/数字存储示波器/scanwave/CONV_SINGLE.vhd" 22 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "TEMP\[7\] CONV_SINGLE.vhd(22) " "Info (10041): Inferred latch for \"TEMP\[7\]\" at CONV_SINGLE.vhd(22)" {  } { { "CONV_SINGLE.vhd" "" { Text "I:/数字存储示波器/scanwave/CONV_SINGLE.vhd" 22 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}