test.hier_info

数字示波器的FPGA实现 VHDL编写 Quartus7.1测试通过

address_a[7] => ram_block1a3.PORTAADDR7
address_a[7] => ram_block1a4.PORTAADDR7
address_a[7] => ram_block1a5.PORTAADDR7
address_a[7] => ram_block1a6.PORTAADDR7
address_a[7] => ram_block1a7.PORTAADDR7
address_a[8] => ram_block1a0.PORTAADDR8
address_a[8] => ram_block1a1.PORTAADDR8
address_a[8] => ram_block1a2.PORTAADDR8
address_a[8] => ram_block1a3.PORTAADDR8
address_a[8] => ram_block1a4.PORTAADDR8
address_a[8] => ram_block1a5.PORTAADDR8
address_a[8] => ram_block1a6.PORTAADDR8
address_a[8] => ram_block1a7.PORTAADDR8
address_a[9] => ram_block1a0.PORTAADDR9
address_a[9] => ram_block1a1.PORTAADDR9
address_a[9] => ram_block1a2.PORTAADDR9
address_a[9] => ram_block1a3.PORTAADDR9
address_a[9] => ram_block1a4.PORTAADDR9
address_a[9] => ram_block1a5.PORTAADDR9
address_a[9] => ram_block1a6.PORTAADDR9
address_a[9] => ram_block1a7.PORTAADDR9
address_a[10] => ram_block1a0.PORTAADDR10
address_a[10] => ram_block1a1.PORTAADDR10
address_a[10] => ram_block1a2.PORTAADDR10
address_a[10] => ram_block1a3.PORTAADDR10
address_a[10] => ram_block1a4.PORTAADDR10
address_a[10] => ram_block1a5.PORTAADDR10
address_a[10] => ram_block1a6.PORTAADDR10
address_a[10] => ram_block1a7.PORTAADDR10
address_b[0] => ram_block1a0.PORTBADDR
address_b[0] => ram_block1a1.PORTBADDR
address_b[0] => ram_block1a2.PORTBADDR
address_b[0] => ram_block1a3.PORTBADDR
address_b[0] => ram_block1a4.PORTBADDR
address_b[0] => ram_block1a5.PORTBADDR
address_b[0] => ram_block1a6.PORTBADDR
address_b[0] => ram_block1a7.PORTBADDR
address_b[1] => ram_block1a0.PORTBADDR1
address_b[1] => ram_block1a1.PORTBADDR1
address_b[1] => ram_block1a2.PORTBADDR1
address_b[1] => ram_block1a3.PORTBADDR1
address_b[1] => ram_block1a4.PORTBADDR1
address_b[1] => ram_block1a5.PORTBADDR1
address_b[1] => ram_block1a6.PORTBADDR1
address_b[1] => ram_block1a7.PORTBADDR1
address_b[2] => ram_block1a0.PORTBADDR2
address_b[2] => ram_block1a1.PORTBADDR2
address_b[2] => ram_block1a2.PORTBADDR2
address_b[2] => ram_block1a3.PORTBADDR2
address_b[2] => ram_block1a4.PORTBADDR2
address_b[2] => ram_block1a5.PORTBADDR2
address_b[2] => ram_block1a6.PORTBADDR2
address_b[2] => ram_block1a7.PORTBADDR2
address_b[3] => ram_block1a0.PORTBADDR3
address_b[3] => ram_block1a1.PORTBADDR3
address_b[3] => ram_block1a2.PORTBADDR3
address_b[3] => ram_block1a3.PORTBADDR3
address_b[3] => ram_block1a4.PORTBADDR3
address_b[3] => ram_block1a5.PORTBADDR3
address_b[3] => ram_block1a6.PORTBADDR3
address_b[3] => ram_block1a7.PORTBADDR3
address_b[4] => ram_block1a0.PORTBADDR4
address_b[4] => ram_block1a1.PORTBADDR4
address_b[4] => ram_block1a2.PORTBADDR4
address_b[4] => ram_block1a3.PORTBADDR4
address_b[4] => ram_block1a4.PORTBADDR4
address_b[4] => ram_block1a5.PORTBADDR4
address_b[4] => ram_block1a6.PORTBADDR4
address_b[4] => ram_block1a7.PORTBADDR4
address_b[5] => ram_block1a0.PORTBADDR5
address_b[5] => ram_block1a1.PORTBADDR5
address_b[5] => ram_block1a2.PORTBADDR5
address_b[5] => ram_block1a3.PORTBADDR5
address_b[5] => ram_block1a4.PORTBADDR5
address_b[5] => ram_block1a5.PORTBADDR5
address_b[5] => ram_block1a6.PORTBADDR5
address_b[5] => ram_block1a7.PORTBADDR5
address_b[6] => ram_block1a0.PORTBADDR6
address_b[6] => ram_block1a1.PORTBADDR6
address_b[6] => ram_block1a2.PORTBADDR6
address_b[6] => ram_block1a3.PORTBADDR6
address_b[6] => ram_block1a4.PORTBADDR6
address_b[6] => ram_block1a5.PORTBADDR6
address_b[6] => ram_block1a6.PORTBADDR6
address_b[6] => ram_block1a7.PORTBADDR6
address_b[7] => ram_block1a0.PORTBADDR7
address_b[7] => ram_block1a1.PORTBADDR7
address_b[7] => ram_block1a2.PORTBADDR7
address_b[7] => ram_block1a3.PORTBADDR7
address_b[7] => ram_block1a4.PORTBADDR7
address_b[7] => ram_block1a5.PORTBADDR7
address_b[7] => ram_block1a6.PORTBADDR7
address_b[7] => ram_block1a7.PORTBADDR7
address_b[8] => ram_block1a0.PORTBADDR8
address_b[8] => ram_block1a1.PORTBADDR8
address_b[8] => ram_block1a2.PORTBADDR8
address_b[8] => ram_block1a3.PORTBADDR8
address_b[8] => ram_block1a4.PORTBADDR8
address_b[8] => ram_block1a5.PORTBADDR8
address_b[8] => ram_block1a6.PORTBADDR8
address_b[8] => ram_block1a7.PORTBADDR8
address_b[9] => ram_block1a0.PORTBADDR9
address_b[9] => ram_block1a1.PORTBADDR9
address_b[9] => ram_block1a2.PORTBADDR9
address_b[9] => ram_block1a3.PORTBADDR9
address_b[9] => ram_block1a4.PORTBADDR9
address_b[9] => ram_block1a5.PORTBADDR9
address_b[9] => ram_block1a6.PORTBADDR9
address_b[9] => ram_block1a7.PORTBADDR9
address_b[10] => ram_block1a0.PORTBADDR10
address_b[10] => ram_block1a1.PORTBADDR10
address_b[10] => ram_block1a2.PORTBADDR10
address_b[10] => ram_block1a3.PORTBADDR10
address_b[10] => ram_block1a4.PORTBADDR10
address_b[10] => ram_block1a5.PORTBADDR10
address_b[10] => ram_block1a6.PORTBADDR10
address_b[10] => ram_block1a7.PORTBADDR10
clock0 => ram_block1a0.CLK0
clock0 => ram_block1a1.CLK0
clock0 => ram_block1a2.CLK0
clock0 => ram_block1a3.CLK0
clock0 => ram_block1a4.CLK0
clock0 => ram_block1a5.CLK0
clock0 => ram_block1a6.CLK0
clock0 => ram_block1a7.CLK0
clock1 => ram_block1a0.CLK1
clock1 => ram_block1a1.CLK1
clock1 => ram_block1a2.CLK1
clock1 => ram_block1a3.CLK1
clock1 => ram_block1a4.CLK1
clock1 => ram_block1a5.CLK1
clock1 => ram_block1a6.CLK1
clock1 => ram_block1a7.CLK1
data_a[0] => ram_block1a0.PORTADATAIN
data_a[1] => ram_block1a1.PORTADATAIN
data_a[2] => ram_block1a2.PORTADATAIN
data_a[3] => ram_block1a3.PORTADATAIN
data_a[4] => ram_block1a4.PORTADATAIN
data_a[5] => ram_block1a5.PORTADATAIN
data_a[6] => ram_block1a6.PORTADATAIN
data_a[7] => ram_block1a7.PORTADATAIN
q_b[0] <= ram_block1a0.PORTBDATAOUT
q_b[1] <= ram_block1a1.PORTBDATAOUT
q_b[2] <= ram_block1a2.PORTBDATAOUT
q_b[3] <= ram_block1a3.PORTBDATAOUT
q_b[4] <= ram_block1a4.PORTBDATAOUT
q_b[5] <= ram_block1a5.PORTBDATAOUT
q_b[6] <= ram_block1a6.PORTBDATAOUT
q_b[7] <= ram_block1a7.PORTBDATAOUT
wren_a => ram_block1a0.PORTAWE
wren_a => ram_block1a1.PORTAWE
wren_a => ram_block1a2.PORTAWE
wren_a => ram_block1a3.PORTAWE
wren_a => ram_block1a4.PORTAWE
wren_a => ram_block1a5.PORTAWE
wren_a => ram_block1a6.PORTAWE
wren_a => ram_block1a7.PORTAWE


|TEST|GET_RDADDR:inst3
CLK => COUNTER[9].CLK
CLK => COUNTER[8].CLK
CLK => COUNTER[7].CLK
CLK => COUNTER[6].CLK
CLK => COUNTER[5].CLK
CLK => COUNTER[4].CLK
CLK => COUNTER[3].CLK
CLK => COUNTER[2].CLK
CLK => COUNTER[1].CLK
CLK => COUNTER[0].CLK
CLK => COUNTER[10].CLK
CLR => COUNTER[9].ACLR
CLR => COUNTER[8].ACLR
CLR => COUNTER[7].ACLR
CLR => COUNTER[6].ACLR
CLR => COUNTER[5].ACLR
CLR => COUNTER[4].ACLR
CLR => COUNTER[3].ACLR
CLR => COUNTER[2].ACLR
CLR => COUNTER[1].ACLR
CLR => COUNTER[0].ACLR
CLR => COUNTER[10].ACLR
Q[0] <= COUNTER[0].DB_MAX_OUTPUT_PORT_TYPE
Q[1] <= COUNTER[1].DB_MAX_OUTPUT_PORT_TYPE
Q[2] <= COUNTER[2].DB_MAX_OUTPUT_PORT_TYPE
Q[3] <= COUNTER[3].DB_MAX_OUTPUT_PORT_TYPE
Q[4] <= COUNTER[4].DB_MAX_OUTPUT_PORT_TYPE
Q[5] <= COUNTER[5].DB_MAX_OUTPUT_PORT_TYPE
Q[6] <= COUNTER[6].DB_MAX_OUTPUT_PORT_TYPE
Q[7] <= COUNTER[7].DB_MAX_OUTPUT_PORT_TYPE
Q[8] <= COUNTER[8].DB_MAX_OUTPUT_PORT_TYPE
Q[9] <= COUNTER[9].DB_MAX_OUTPUT_PORT_TYPE
Q[10] <= COUNTER[10].DB_MAX_OUTPUT_PORT_TYPE


|TEST|generator_accB:inst7
CLK => REG_Q[20].CLK
CLK => REG_Q[19].CLK
CLK => REG_Q[18].CLK
CLK => REG_Q[17].CLK
CLK => REG_Q[16].CLK
CLK => REG_Q[15].CLK
CLK => REG_Q[14].CLK
CLK => REG_Q[13].CLK
CLK => REG_Q[12].CLK
CLK => REG_Q[11].CLK
CLK => REG_Q[10].CLK
CLK => REG_Q[9].CLK
CLK => REG_Q[8].CLK
CLK => REG_Q[7].CLK
CLK => REG_Q[6].CLK
CLK => REG_Q[5].CLK
CLK => REG_Q[4].CLK
CLK => REG_Q[3].CLK
CLK => REG_Q[2].CLK
CLK => REG_Q[1].CLK
CLK => REG_Q[0].CLK
CLK => REG_Q[21].CLK
CLR => REG_Q[20].ACLR
CLR => REG_Q[19].ACLR
CLR => REG_Q[18].ACLR
CLR => REG_Q[17].ACLR
CLR => REG_Q[16].ACLR
CLR => REG_Q[15].ACLR
CLR => REG_Q[14].ACLR
CLR => REG_Q[13].ACLR
CLR => REG_Q[12].ACLR
CLR => REG_Q[11].ACLR
CLR => REG_Q[10].ACLR
CLR => REG_Q[9].ACLR
CLR => REG_Q[8].ACLR
CLR => REG_Q[7].ACLR
CLR => REG_Q[6].ACLR
CLR => REG_Q[5].ACLR
CLR => REG_Q[4].ACLR
CLR => REG_Q[3].ACLR
CLR => REG_Q[2].ACLR
CLR => REG_Q[1].ACLR
CLR => REG_Q[0].ACLR
CLR => REG_Q[21].ACLR
A[0] => add~0.IN22
A[1] => add~0.IN21
A[2] => add~0.IN20
A[3] => add~0.IN19
A[4] => add~0.IN18
A[5] => add~0.IN17
A[6] => add~0.IN16
A[7] => add~0.IN15
A[8] => add~0.IN14
A[9] => add~0.IN13
A[10] => add~0.IN12
A[11] => add~0.IN11
A[12] => add~0.IN10
A[13] => add~0.IN9
A[14] => add~0.IN8
A[15] => add~0.IN7
A[16] => add~0.IN6
A[17] => add~0.IN5
A[18] => add~0.IN4
A[19] => add~0.IN3
A[20] => add~0.IN2
A[21] => add~0.IN1
START <= reduce_nor~0.DB_MAX_OUTPUT_PORT_TYPE
Q[0] <= REG_Q[14].DB_MAX_OUTPUT_PORT_TYPE
Q[1] <= REG_Q[15].DB_MAX_OUTPUT_PORT_TYPE
Q[2] <= REG_Q[16].DB_MAX_OUTPUT_PORT_TYPE
Q[3] <= REG_Q[17].DB_MAX_OUTPUT_PORT_TYPE
Q[4] <= REG_Q[18].DB_MAX_OUTPUT_PORT_TYPE
Q[5] <= REG_Q[19].DB_MAX_OUTPUT_PORT_TYPE
Q[6] <= REG_Q[20].DB_MAX_OUTPUT_PORT_TYPE
Q[7] <= REG_Q[21].DB_MAX_OUTPUT_PORT_TYPE


|TEST|FREDEVIDER8:78
CLKIN => COUNTER[5].CLK
CLKIN => COUNTER[4].CLK
CLKIN => COUNTER[3].CLK
CLKIN => COUNTER[2].CLK
CLKIN => COUNTER[1].CLK
CLKIN => COUNTER[0].CLK
CLKIN => CLK.CLK
CLKIN => COUNTER[6].CLK
CLKOUT <= CLK.DB_MAX_OUTPUT_PORT_TYPE


|TEST|generator_reg81:79
CLR => TEMP_Q_1[6].ACLR
CLR => TEMP_Q_1[5].ACLR
CLR => TEMP_Q_1[4].ACLR
CLR => TEMP_Q_1[3].ACLR
CLR => TEMP_Q_1[2].ACLR
CLR => TEMP_Q_1[1].ACLR
CLR => TEMP_Q_1[0].ACLR
CLR => TEMP_Q_1[7].ACLR
CLKK => TEMP_Q_1[6].CLK
CLKK => TEMP_Q_1[5].CLK
CLKK => TEMP_Q_1[4].CLK
CLKK => TEMP_Q_1[3].CLK
CLKK => TEMP_Q_1[2].CLK
CLKK => TEMP_Q_1[1].CLK
CLKK => TEMP_Q_1[0].CLK
CLKK => TEMP_Q_1[7].CLK
DATA[0] => TEMP_Q_1[0].DATAIN
DATA[1] => TEMP_Q_1[1].DATAIN
DATA[2] => TEMP_Q_1[2].DATAIN
DATA[3] => TEMP_Q_1[3].DATAIN
DATA[4] => TEMP_Q_1[4].DATAIN
DATA[5] => TEMP_Q_1[5].DATAIN
DATA[6] => TEMP_Q_1[6].DATAIN
DATA[7] => TEMP_Q_1[7].DATAIN
Q1[0] <= TEMP_Q_1[0].DB_MAX_OUTPUT_PORT_TYPE
Q1[1] <= TEMP_Q_1[1].DB_MAX_OUTPUT_PORT_TYPE
Q1[2] <= TEMP_Q_1[2].DB_MAX_OUTPUT_PORT_TYPE
Q1[3] <= TEMP_Q_1[3].DB_MAX_OUTPUT_PORT_TYPE
Q1[4] <= TEMP_Q_1[4].DB_MAX_OUTPUT_PORT_TYPE
Q1[5] <= TEMP_Q_1[5].DB_MAX_OUTPUT_PORT_TYPE
Q1[6] <= TEMP_Q_1[6].DB_MAX_OUTPUT_PORT_TYPE
Q1[7] <= TEMP_Q_1[7].DB_MAX_OUTPUT_PORT_TYPE


|TEST|generator_add:inst8
A[0] => add~0.IN8
A[1] => add~0.IN7
A[2] => add~0.IN6
A[3] => add~0.IN5
A[4] => add~0.IN4
A[5] => add~0.IN3
A[6] => add~0.IN2
A[7] => add~0.IN1
B[0] => add~0.IN16
B[1] => add~0.IN15
B[2] => add~0.IN14
B[3] => add~0.IN13
B[4] => add~0.IN12
B[5] => add~0.IN11
B[6] => add~0.IN10
B[7] => add~0.IN9
Q[0] <= add~0.DB_MAX_OUTPUT_PORT_TYPE
Q[1] <= add~0.DB_MAX_OUTPUT_PORT_TYPE
Q[2] <= add~0.DB_MAX_OUTPUT_PORT_TYPE
Q[3] <= Q~4.DB_MAX_OUTPUT_PORT_TYPE
Q[4] <= Q~3.DB_MAX_OUTPUT_PORT_TYPE
Q[5] <= Q~2.DB_MAX_OUTPUT_PORT_TYPE
Q[6] <= Q~1.DB_MAX_OUTPUT_PORT_TYPE
Q[7] <= Q~0.DB_MAX_OUTPUT_PORT_TYPE