test.hier_info

数字示波器的FPGA实现 VHDL编写 Quartus7.1测试通过

CLK => RAMTMP1[1].CLK
CLK => RAMTMP1[0].CLK
CLK => RAMTMP2[7].CLK
CLK => RAMTMP2[6].CLK
CLK => RAMTMP2[5].CLK
CLK => RAMTMP2[4].CLK
CLK => RAMTMP2[3].CLK
CLK => RAMTMP2[2].CLK
CLK => RAMTMP2[1].CLK
CLK => RAMTMP2[0].CLK
CLK => RAMTMP6[0].CLK
CLK => RAMTMP7[7].CLK
CLK => RAMTMP7[6].CLK
CLK => RAMTMP7[5].CLK
CLK => RAMTMP7[4].CLK
CLK => RAMTMP7[3].CLK
CLK => RAMTMP7[2].CLK
CLK => RAMTMP7[1].CLK
CLK => RAMTMP7[0].CLK
CLK => RAMTMP8[0].CLK
CLK => RAMTMP9[7].CLK
CLK => RAMTMP9[6].CLK
CLK => RAMTMP9[5].CLK
CLK => RAMTMP9[4].CLK
CLK => RAMTMP9[3].CLK
CLK => RAMTMP9[2].CLK
CLK => RAMTMP9[1].CLK
CLK => RAMTMP9[0].CLK
CLK => RAMTMP10[7].CLK
CLK => RAMTMP10[6].CLK
CLK => RAMTMP10[5].CLK
CLK => RAMTMP10[4].CLK
CLK => RAMTMP10[3].CLK
CLK => RAMTMP10[2].CLK
CLK => RAMTMP10[1].CLK
CLK => RAMTMP10[0].CLK
CLK => RAMTMP11[7].CLK
CLK => RAMTMP11[6].CLK
CLK => RAMTMP11[5].CLK
CLK => RAMTMP11[4].CLK
CLK => RAMTMP11[3].CLK
CLK => RAMTMP11[2].CLK
CLK => RAMTMP11[1].CLK
CLK => RAMTMP11[0].CLK
CLK => RAMTMP0[7].CLK
GX <= GX~reg0.DB_MAX_OUTPUT_PORT_TYPE
CLR <= TMP.DB_MAX_OUTPUT_PORT_TYPE
SINGLE <= RAMTMP6[0].DB_MAX_OUTPUT_PORT_TYPE
LOCKS <= RAMTMP8[0].DB_MAX_OUTPUT_PORT_TYPE
TRIGV[0] <= RAMTMP7[0].DB_MAX_OUTPUT_PORT_TYPE
TRIGV[1] <= RAMTMP7[1].DB_MAX_OUTPUT_PORT_TYPE
TRIGV[2] <= RAMTMP7[2].DB_MAX_OUTPUT_PORT_TYPE
TRIGV[3] <= RAMTMP7[3].DB_MAX_OUTPUT_PORT_TYPE
TRIGV[4] <= RAMTMP7[4].DB_MAX_OUTPUT_PORT_TYPE
TRIGV[5] <= RAMTMP7[5].DB_MAX_OUTPUT_PORT_TYPE
TRIGV[6] <= RAMTMP7[6].DB_MAX_OUTPUT_PORT_TYPE
TRIGV[7] <= RAMTMP7[7].DB_MAX_OUTPUT_PORT_TYPE
PDATA[0] <= RAMTMP11[0].DB_MAX_OUTPUT_PORT_TYPE
PDATA[1] <= RAMTMP11[1].DB_MAX_OUTPUT_PORT_TYPE
PDATA[2] <= RAMTMP11[2].DB_MAX_OUTPUT_PORT_TYPE
PDATA[3] <= RAMTMP11[3].DB_MAX_OUTPUT_PORT_TYPE
PDATA[4] <= RAMTMP11[4].DB_MAX_OUTPUT_PORT_TYPE
PDATA[5] <= RAMTMP11[5].DB_MAX_OUTPUT_PORT_TYPE
PDATA[6] <= RAMTMP11[6].DB_MAX_OUTPUT_PORT_TYPE
PDATA[7] <= RAMTMP11[7].DB_MAX_OUTPUT_PORT_TYPE
FDATA[0] <= RAMTMP10[0].DB_MAX_OUTPUT_PORT_TYPE
FDATA[1] <= RAMTMP10[1].DB_MAX_OUTPUT_PORT_TYPE
FDATA[2] <= RAMTMP10[2].DB_MAX_OUTPUT_PORT_TYPE
FDATA[3] <= RAMTMP10[3].DB_MAX_OUTPUT_PORT_TYPE
FDATA[4] <= RAMTMP10[4].DB_MAX_OUTPUT_PORT_TYPE
FDATA[5] <= RAMTMP10[5].DB_MAX_OUTPUT_PORT_TYPE
FDATA[6] <= RAMTMP10[6].DB_MAX_OUTPUT_PORT_TYPE
FDATA[7] <= RAMTMP10[7].DB_MAX_OUTPUT_PORT_TYPE
FDATA[8] <= RAMTMP9[0].DB_MAX_OUTPUT_PORT_TYPE
FDATA[9] <= RAMTMP9[1].DB_MAX_OUTPUT_PORT_TYPE
FDATA[10] <= RAMTMP9[2].DB_MAX_OUTPUT_PORT_TYPE
FDATA[11] <= RAMTMP9[3].DB_MAX_OUTPUT_PORT_TYPE
FDATA[12] <= RAMTMP9[4].DB_MAX_OUTPUT_PORT_TYPE
FDATA[13] <= RAMTMP9[5].DB_MAX_OUTPUT_PORT_TYPE
FDATA[14] <= RAMTMP9[6].DB_MAX_OUTPUT_PORT_TYPE
FDATA[15] <= RAMTMP9[7].DB_MAX_OUTPUT_PORT_TYPE
FDATA[16] <= <GND>
FDATA[17] <= <GND>
FDATA[18] <= <GND>
FDATA[19] <= <GND>
FDATA[20] <= <GND>
FDATA[21] <= <GND>
POSX_A[0] <= RAMTMP2[0].DB_MAX_OUTPUT_PORT_TYPE
POSX_A[1] <= RAMTMP2[1].DB_MAX_OUTPUT_PORT_TYPE
POSX_A[2] <= RAMTMP2[2].DB_MAX_OUTPUT_PORT_TYPE
POSX_A[3] <= RAMTMP2[3].DB_MAX_OUTPUT_PORT_TYPE
POSX_A[4] <= RAMTMP2[4].DB_MAX_OUTPUT_PORT_TYPE
POSX_A[5] <= RAMTMP2[5].DB_MAX_OUTPUT_PORT_TYPE
POSX_A[6] <= RAMTMP2[6].DB_MAX_OUTPUT_PORT_TYPE
POSX_A[7] <= RAMTMP2[7].DB_MAX_OUTPUT_PORT_TYPE
P2[0] => ~NO_FANOUT~
P2[1] => ~NO_FANOUT~
P2[2] => ~NO_FANOUT~
P2[3] => ~NO_FANOUT~
P2[4] => ~NO_FANOUT~
CS => process1~0.IN1
CS => process2~0.IN0


|TEST|BUSTRI:inst11
data[0] => lpm_bustri:lpm_bustri_component.data[0]
data[1] => lpm_bustri:lpm_bustri_component.data[1]
data[2] => lpm_bustri:lpm_bustri_component.data[2]
data[3] => lpm_bustri:lpm_bustri_component.data[3]
data[4] => lpm_bustri:lpm_bustri_component.data[4]
data[5] => lpm_bustri:lpm_bustri_component.data[5]
data[6] => lpm_bustri:lpm_bustri_component.data[6]
data[7] => lpm_bustri:lpm_bustri_component.data[7]
enabledt => lpm_bustri:lpm_bustri_component.enabledt
enabletr => lpm_bustri:lpm_bustri_component.enabletr
tridata[0] <= lpm_bustri:lpm_bustri_component.tridata[0]
tridata[1] <= lpm_bustri:lpm_bustri_component.tridata[1]
tridata[2] <= lpm_bustri:lpm_bustri_component.tridata[2]
tridata[3] <= lpm_bustri:lpm_bustri_component.tridata[3]
tridata[4] <= lpm_bustri:lpm_bustri_component.tridata[4]
tridata[5] <= lpm_bustri:lpm_bustri_component.tridata[5]
tridata[6] <= lpm_bustri:lpm_bustri_component.tridata[6]
tridata[7] <= lpm_bustri:lpm_bustri_component.tridata[7]
result[0] <= lpm_bustri:lpm_bustri_component.result[0]
result[1] <= lpm_bustri:lpm_bustri_component.result[1]
result[2] <= lpm_bustri:lpm_bustri_component.result[2]
result[3] <= lpm_bustri:lpm_bustri_component.result[3]
result[4] <= lpm_bustri:lpm_bustri_component.result[4]
result[5] <= lpm_bustri:lpm_bustri_component.result[5]
result[6] <= lpm_bustri:lpm_bustri_component.result[6]
result[7] <= lpm_bustri:lpm_bustri_component.result[7]


|TEST|BUSTRI:inst11|lpm_bustri:lpm_bustri_component
tridata[0] <= dout[0]
tridata[1] <= dout[1]
tridata[2] <= dout[2]
tridata[3] <= dout[3]
tridata[4] <= dout[4]
tridata[5] <= dout[5]
tridata[6] <= dout[6]
tridata[7] <= dout[7]
data[0] => dout[0].DATAIN
data[1] => dout[1].DATAIN
data[2] => dout[2].DATAIN
data[3] => dout[3].DATAIN
data[4] => dout[4].DATAIN
data[5] => dout[5].DATAIN
data[6] => dout[6].DATAIN
data[7] => dout[7].DATAIN
enabletr => din[7].OE
enabletr => din[6].OE
enabletr => din[5].OE
enabletr => din[4].OE
enabletr => din[3].OE
enabletr => din[2].OE
enabletr => din[1].OE
enabletr => din[0].OE
enabledt => dout[7].OE
enabledt => dout[6].OE
enabledt => dout[5].OE
enabledt => dout[4].OE
enabledt => dout[3].OE
enabledt => dout[2].OE
enabledt => dout[1].OE
enabledt => dout[0].OE
result[0] <= din[0].DB_MAX_OUTPUT_PORT_TYPE
result[1] <= din[1].DB_MAX_OUTPUT_PORT_TYPE
result[2] <= din[2].DB_MAX_OUTPUT_PORT_TYPE
result[3] <= din[3].DB_MAX_OUTPUT_PORT_TYPE
result[4] <= din[4].DB_MAX_OUTPUT_PORT_TYPE
result[5] <= din[5].DB_MAX_OUTPUT_PORT_TYPE
result[6] <= din[6].DB_MAX_OUTPUT_PORT_TYPE
result[7] <= din[7].DB_MAX_OUTPUT_PORT_TYPE


|TEST|dram:inst
data[0] => altsyncram:altsyncram_component.data_a[0]
data[1] => altsyncram:altsyncram_component.data_a[1]
data[2] => altsyncram:altsyncram_component.data_a[2]
data[3] => altsyncram:altsyncram_component.data_a[3]
data[4] => altsyncram:altsyncram_component.data_a[4]
data[5] => altsyncram:altsyncram_component.data_a[5]
data[6] => altsyncram:altsyncram_component.data_a[6]
data[7] => altsyncram:altsyncram_component.data_a[7]
wren => altsyncram:altsyncram_component.wren_a
wraddress[0] => altsyncram:altsyncram_component.address_a[0]
wraddress[1] => altsyncram:altsyncram_component.address_a[1]
wraddress[2] => altsyncram:altsyncram_component.address_a[2]
wraddress[3] => altsyncram:altsyncram_component.address_a[3]
wraddress[4] => altsyncram:altsyncram_component.address_a[4]
wraddress[5] => altsyncram:altsyncram_component.address_a[5]
wraddress[6] => altsyncram:altsyncram_component.address_a[6]
wraddress[7] => altsyncram:altsyncram_component.address_a[7]
wraddress[8] => altsyncram:altsyncram_component.address_a[8]
wraddress[9] => altsyncram:altsyncram_component.address_a[9]
wraddress[10] => altsyncram:altsyncram_component.address_a[10]
rdaddress[0] => altsyncram:altsyncram_component.address_b[0]
rdaddress[1] => altsyncram:altsyncram_component.address_b[1]
rdaddress[2] => altsyncram:altsyncram_component.address_b[2]
rdaddress[3] => altsyncram:altsyncram_component.address_b[3]
rdaddress[4] => altsyncram:altsyncram_component.address_b[4]
rdaddress[5] => altsyncram:altsyncram_component.address_b[5]
rdaddress[6] => altsyncram:altsyncram_component.address_b[6]
rdaddress[7] => altsyncram:altsyncram_component.address_b[7]
rdaddress[8] => altsyncram:altsyncram_component.address_b[8]
rdaddress[9] => altsyncram:altsyncram_component.address_b[9]
rdaddress[10] => altsyncram:altsyncram_component.address_b[10]
wrclock => altsyncram:altsyncram_component.clock0
rdclock => altsyncram:altsyncram_component.clock1
q[0] <= altsyncram:altsyncram_component.q_b[0]
q[1] <= altsyncram:altsyncram_component.q_b[1]
q[2] <= altsyncram:altsyncram_component.q_b[2]
q[3] <= altsyncram:altsyncram_component.q_b[3]
q[4] <= altsyncram:altsyncram_component.q_b[4]
q[5] <= altsyncram:altsyncram_component.q_b[5]
q[6] <= altsyncram:altsyncram_component.q_b[6]
q[7] <= altsyncram:altsyncram_component.q_b[7]


|TEST|dram:inst|altsyncram:altsyncram_component
wren_a => altsyncram_8r81:auto_generated.wren_a
wren_b => ~NO_FANOUT~
rden_b => ~NO_FANOUT~
data_a[0] => altsyncram_8r81:auto_generated.data_a[0]
data_a[1] => altsyncram_8r81:auto_generated.data_a[1]
data_a[2] => altsyncram_8r81:auto_generated.data_a[2]
data_a[3] => altsyncram_8r81:auto_generated.data_a[3]
data_a[4] => altsyncram_8r81:auto_generated.data_a[4]
data_a[5] => altsyncram_8r81:auto_generated.data_a[5]
data_a[6] => altsyncram_8r81:auto_generated.data_a[6]
data_a[7] => altsyncram_8r81:auto_generated.data_a[7]
data_b[0] => ~NO_FANOUT~
data_b[1] => ~NO_FANOUT~
data_b[2] => ~NO_FANOUT~
data_b[3] => ~NO_FANOUT~
data_b[4] => ~NO_FANOUT~
data_b[5] => ~NO_FANOUT~
data_b[6] => ~NO_FANOUT~
data_b[7] => ~NO_FANOUT~
address_a[0] => altsyncram_8r81:auto_generated.address_a[0]
address_a[1] => altsyncram_8r81:auto_generated.address_a[1]
address_a[2] => altsyncram_8r81:auto_generated.address_a[2]
address_a[3] => altsyncram_8r81:auto_generated.address_a[3]
address_a[4] => altsyncram_8r81:auto_generated.address_a[4]
address_a[5] => altsyncram_8r81:auto_generated.address_a[5]
address_a[6] => altsyncram_8r81:auto_generated.address_a[6]
address_a[7] => altsyncram_8r81:auto_generated.address_a[7]
address_a[8] => altsyncram_8r81:auto_generated.address_a[8]
address_a[9] => altsyncram_8r81:auto_generated.address_a[9]
address_a[10] => altsyncram_8r81:auto_generated.address_a[10]
address_b[0] => altsyncram_8r81:auto_generated.address_b[0]
address_b[1] => altsyncram_8r81:auto_generated.address_b[1]
address_b[2] => altsyncram_8r81:auto_generated.address_b[2]
address_b[3] => altsyncram_8r81:auto_generated.address_b[3]
address_b[4] => altsyncram_8r81:auto_generated.address_b[4]
address_b[5] => altsyncram_8r81:auto_generated.address_b[5]
address_b[6] => altsyncram_8r81:auto_generated.address_b[6]
address_b[7] => altsyncram_8r81:auto_generated.address_b[7]
address_b[8] => altsyncram_8r81:auto_generated.address_b[8]
address_b[9] => altsyncram_8r81:auto_generated.address_b[9]
address_b[10] => altsyncram_8r81:auto_generated.address_b[10]
addressstall_a => ~NO_FANOUT~
addressstall_b => ~NO_FANOUT~
clock0 => altsyncram_8r81:auto_generated.clock0
clock1 => altsyncram_8r81:auto_generated.clock1
clocken0 => ~NO_FANOUT~
clocken1 => ~NO_FANOUT~
aclr0 => ~NO_FANOUT~
aclr1 => ~NO_FANOUT~
byteena_a[0] => ~NO_FANOUT~
byteena_b[0] => ~NO_FANOUT~
q_a[0] <= <UNC>
q_a[1] <= <UNC>
q_a[2] <= <UNC>
q_a[3] <= <UNC>
q_a[4] <= <UNC>
q_a[5] <= <UNC>
q_a[6] <= <UNC>
q_a[7] <= <UNC>
q_b[0] <= altsyncram_8r81:auto_generated.q_b[0]
q_b[1] <= altsyncram_8r81:auto_generated.q_b[1]
q_b[2] <= altsyncram_8r81:auto_generated.q_b[2]
q_b[3] <= altsyncram_8r81:auto_generated.q_b[3]
q_b[4] <= altsyncram_8r81:auto_generated.q_b[4]
q_b[5] <= altsyncram_8r81:auto_generated.q_b[5]
q_b[6] <= altsyncram_8r81:auto_generated.q_b[6]
q_b[7] <= altsyncram_8r81:auto_generated.q_b[7]


|TEST|dram:inst|altsyncram:altsyncram_component|altsyncram_8r81:auto_generated
address_a[0] => ram_block1a0.PORTAADDR
address_a[0] => ram_block1a1.PORTAADDR
address_a[0] => ram_block1a2.PORTAADDR
address_a[0] => ram_block1a3.PORTAADDR
address_a[0] => ram_block1a4.PORTAADDR
address_a[0] => ram_block1a5.PORTAADDR
address_a[0] => ram_block1a6.PORTAADDR
address_a[0] => ram_block1a7.PORTAADDR
address_a[1] => ram_block1a0.PORTAADDR1
address_a[1] => ram_block1a1.PORTAADDR1
address_a[1] => ram_block1a2.PORTAADDR1
address_a[1] => ram_block1a3.PORTAADDR1
address_a[1] => ram_block1a4.PORTAADDR1
address_a[1] => ram_block1a5.PORTAADDR1
address_a[1] => ram_block1a6.PORTAADDR1
address_a[1] => ram_block1a7.PORTAADDR1
address_a[2] => ram_block1a0.PORTAADDR2
address_a[2] => ram_block1a1.PORTAADDR2
address_a[2] => ram_block1a2.PORTAADDR2
address_a[2] => ram_block1a3.PORTAADDR2
address_a[2] => ram_block1a4.PORTAADDR2
address_a[2] => ram_block1a5.PORTAADDR2
address_a[2] => ram_block1a6.PORTAADDR2
address_a[2] => ram_block1a7.PORTAADDR2
address_a[3] => ram_block1a0.PORTAADDR3
address_a[3] => ram_block1a1.PORTAADDR3
address_a[3] => ram_block1a2.PORTAADDR3
address_a[3] => ram_block1a3.PORTAADDR3
address_a[3] => ram_block1a4.PORTAADDR3
address_a[3] => ram_block1a5.PORTAADDR3
address_a[3] => ram_block1a6.PORTAADDR3
address_a[3] => ram_block1a7.PORTAADDR3
address_a[4] => ram_block1a0.PORTAADDR4
address_a[4] => ram_block1a1.PORTAADDR4
address_a[4] => ram_block1a2.PORTAADDR4
address_a[4] => ram_block1a3.PORTAADDR4
address_a[4] => ram_block1a4.PORTAADDR4
address_a[4] => ram_block1a5.PORTAADDR4
address_a[4] => ram_block1a6.PORTAADDR4
address_a[4] => ram_block1a7.PORTAADDR4
address_a[5] => ram_block1a0.PORTAADDR5
address_a[5] => ram_block1a1.PORTAADDR5
address_a[5] => ram_block1a2.PORTAADDR5
address_a[5] => ram_block1a3.PORTAADDR5
address_a[5] => ram_block1a4.PORTAADDR5
address_a[5] => ram_block1a5.PORTAADDR5
address_a[5] => ram_block1a6.PORTAADDR5
address_a[5] => ram_block1a7.PORTAADDR5
address_a[6] => ram_block1a0.PORTAADDR6
address_a[6] => ram_block1a1.PORTAADDR6
address_a[6] => ram_block1a2.PORTAADDR6
address_a[6] => ram_block1a3.PORTAADDR6
address_a[6] => ram_block1a4.PORTAADDR6
address_a[6] => ram_block1a5.PORTAADDR6
address_a[6] => ram_block1a6.PORTAADDR6
address_a[6] => ram_block1a7.PORTAADDR6
address_a[7] => ram_block1a0.PORTAADDR7
address_a[7] => ram_block1a1.PORTAADDR7
address_a[7] => ram_block1a2.PORTAADDR7