test.hier_info

数字示波器的FPGA实现 VHDL编写 Quartus7.1测试通过

|TEST
XFER <= <GND>
A1 <= MAX114:39.A1
CLK => MAX114:39.CLK
CLK => AD_SRAM:inst2.CLK
CLK => BUS_1:inst9.CLK
CLK => dram:inst.wrclock
CLK => dram:inst.rdclock
CLK => FREDEVIDER8:78.CLKIN
INTN => MAX114:39.INTN
ADIN[0] => MAX114:39.ADIN[0]
ADIN[1] => MAX114:39.ADIN[1]
ADIN[2] => MAX114:39.ADIN[2]
ADIN[3] => MAX114:39.ADIN[3]
ADIN[4] => MAX114:39.ADIN[4]
ADIN[5] => MAX114:39.ADIN[5]
ADIN[6] => MAX114:39.ADIN[6]
ADIN[7] => MAX114:39.ADIN[7]
CSDA2 <= <GND>
CSDA1 <= <GND>
WRDA <= <GND>
A0 <= MAX114:39.A0
CSAD <= MAX114:39.CSAD
RDAD <= MAX114:39.RDAD
DAOUT[0] <= VOLTAGE_CONV:inst4.Q[0]
DAOUT[1] <= VOLTAGE_CONV:inst4.Q[1]
DAOUT[2] <= VOLTAGE_CONV:inst4.Q[2]
DAOUT[3] <= VOLTAGE_CONV:inst4.Q[3]
DAOUT[4] <= VOLTAGE_CONV:inst4.Q[4]
DAOUT[5] <= VOLTAGE_CONV:inst4.Q[5]
DAOUT[6] <= VOLTAGE_CONV:inst4.Q[6]
DAOUT[7] <= VOLTAGE_CONV:inst4.Q[7]
ALE => BUS_1:inst9.ALE
RD => BUS_1:inst9.RD
WR => BUS_1:inst9.WR
CS => BUS_1:inst9.CS
P0[0] <= BUSTRI:inst11.tridata[0]
P0[1] <= BUSTRI:inst11.tridata[1]
P0[2] <= BUSTRI:inst11.tridata[2]
P0[3] <= BUSTRI:inst11.tridata[3]
P0[4] <= BUSTRI:inst11.tridata[4]
P0[5] <= BUSTRI:inst11.tridata[5]
P0[6] <= BUSTRI:inst11.tridata[6]
P0[7] <= BUSTRI:inst11.tridata[7]
P2[0] => BUS_1:inst9.P2[0]
P2[1] => BUS_1:inst9.P2[1]
P2[2] => BUS_1:inst9.P2[2]
P2[3] => BUS_1:inst9.P2[3]
P2[4] => BUS_1:inst9.P2[4]
DAXOUT[0] <= GENERATOR_REG81:79.Q1[0]
DAXOUT[1] <= GENERATOR_REG81:79.Q1[1]
DAXOUT[2] <= GENERATOR_REG81:79.Q1[2]
DAXOUT[3] <= GENERATOR_REG81:79.Q1[3]
DAXOUT[4] <= GENERATOR_REG81:79.Q1[4]
DAXOUT[5] <= GENERATOR_REG81:79.Q1[5]
DAXOUT[6] <= GENERATOR_REG81:79.Q1[6]
DAXOUT[7] <= GENERATOR_REG81:79.Q1[7]


|TEST|MAX114:39
ADIN[0] => Q~7.DATAB
ADIN[0] => PRO~9.DATAIN
ADIN[1] => Q~6.DATAB
ADIN[1] => PRO~8.DATAIN
ADIN[2] => Q~5.DATAB
ADIN[2] => PRO~7.DATAIN
ADIN[3] => Q~4.DATAB
ADIN[3] => PRO~6.DATAIN
ADIN[4] => Q~3.DATAB
ADIN[4] => PRO~5.DATAIN
ADIN[5] => Q~2.DATAB
ADIN[5] => PRO~4.DATAIN
ADIN[6] => Q~1.DATAB
ADIN[6] => PRO~3.DATAIN
ADIN[7] => Q~0.DATAB
ADIN[7] => PRO~2.DATAIN
CLK => CURRENT_STATE~0.IN1
INTN => NEXT_STATE.st1.IN1
INTN => NEXT_STATE.st1.IN2
INTN => NEXT_STATE.st0.IN4
INTN => NEXT_STATE.st2.DATAB
SAVE <= SAVE$latch.DB_MAX_OUTPUT_PORT_TYPE
RDAD <= RD~0.DB_MAX_OUTPUT_PORT_TYPE
CSAD <= RD~0.DB_MAX_OUTPUT_PORT_TYPE
ADOUT[0] <= Q~7.DB_MAX_OUTPUT_PORT_TYPE
ADOUT[1] <= Q~6.DB_MAX_OUTPUT_PORT_TYPE
ADOUT[2] <= Q~5.DB_MAX_OUTPUT_PORT_TYPE
ADOUT[3] <= Q~4.DB_MAX_OUTPUT_PORT_TYPE
ADOUT[4] <= Q~3.DB_MAX_OUTPUT_PORT_TYPE
ADOUT[5] <= Q~2.DB_MAX_OUTPUT_PORT_TYPE
ADOUT[6] <= Q~1.DB_MAX_OUTPUT_PORT_TYPE
ADOUT[7] <= Q~0.DB_MAX_OUTPUT_PORT_TYPE
A0 <= <GND>
A1 <= <GND>


|TEST|VOLTAGE_CONV:inst4
CLKK => TEMP[6].CLK
CLKK => TEMP[5].CLK
CLKK => TEMP[4].CLK
CLKK => TEMP[3].CLK
CLKK => TEMP[2].CLK
CLKK => TEMP[1].CLK
CLKK => TEMP[0].CLK
CLKK => TEMP[7].CLK
DATA[0] => add~0.IN8
DATA[1] => add~0.IN7
DATA[2] => add~0.IN6
DATA[3] => add~0.IN5
DATA[4] => add~0.IN4
DATA[5] => add~0.IN3
DATA[6] => add~0.IN2
DATA[7] => add~0.IN1
POSX_A[0] => add~0.IN16
POSX_A[1] => add~0.IN15
POSX_A[2] => add~0.IN14
POSX_A[3] => add~0.IN13
POSX_A[4] => add~0.IN12
POSX_A[5] => add~0.IN11
POSX_A[6] => add~0.IN10
POSX_A[7] => add~0.IN9
Q[0] <= TEMP[0].DB_MAX_OUTPUT_PORT_TYPE
Q[1] <= TEMP[1].DB_MAX_OUTPUT_PORT_TYPE
Q[2] <= TEMP[2].DB_MAX_OUTPUT_PORT_TYPE
Q[3] <= TEMP[3].DB_MAX_OUTPUT_PORT_TYPE
Q[4] <= TEMP[4].DB_MAX_OUTPUT_PORT_TYPE
Q[5] <= TEMP[5].DB_MAX_OUTPUT_PORT_TYPE
Q[6] <= TEMP[6].DB_MAX_OUTPUT_PORT_TYPE
Q[7] <= TEMP[7].DB_MAX_OUTPUT_PORT_TYPE


|TEST|AD_SRAM:inst2
CLK => cnt2[9].CLK
CLK => cnt2[8].CLK
CLK => cnt2[7].CLK
CLK => cnt2[6].CLK
CLK => cnt2[5].CLK
CLK => cnt2[4].CLK
CLK => cnt2[3].CLK
CLK => cnt2[2].CLK
CLK => cnt2[1].CLK
CLK => cnt2[0].CLK
CLK => cnt[2].CLK
CLK => cnt[1].CLK
CLK => cnt[0].CLK
CLK => WR.CLK
CLK => data[7].CLK
CLK => data[6].CLK
CLK => data[5].CLK
CLK => data[4].CLK
CLK => data[3].CLK
CLK => data[2].CLK
CLK => data[1].CLK
CLK => data[0].CLK
CLK => cnt2[10].CLK
EN => cnt2[9].ACLR
EN => cnt2[8].ACLR
EN => cnt2[7].ACLR
EN => cnt2[6].ACLR
EN => cnt2[5].ACLR
EN => cnt2[4].ACLR
EN => cnt2[3].ACLR
EN => cnt2[2].ACLR
EN => cnt2[1].ACLR
EN => cnt2[0].ACLR
EN => cnt[2].ACLR
EN => cnt[1].ACLR
EN => cnt[0].ACLR
EN => cnt2[10].ACLR
EN => WR.ENA
EN => data[7].ENA
EN => data[6].ENA
EN => data[5].ENA
EN => data[4].ENA
EN => data[3].ENA
EN => data[2].ENA
EN => data[1].ENA
EN => data[0].ENA
SAVE => Mux~3.IN2
TRIGGER => cnt2~0.OUTPUTSELECT
TRIGGER => cnt2~1.OUTPUTSELECT
TRIGGER => cnt2~2.OUTPUTSELECT
TRIGGER => cnt2~3.OUTPUTSELECT
TRIGGER => cnt2~4.OUTPUTSELECT
TRIGGER => cnt2~5.OUTPUTSELECT
TRIGGER => cnt2~6.OUTPUTSELECT
TRIGGER => cnt2~7.OUTPUTSELECT
TRIGGER => cnt2~8.OUTPUTSELECT
TRIGGER => cnt2~9.OUTPUTSELECT
TRIGGER => cnt2~10.OUTPUTSELECT
TRIGGER => cnt~0.DATAB
AIN[0] => Mux~22.IN0
AIN[1] => Mux~21.IN0
AIN[2] => Mux~20.IN0
AIN[3] => Mux~19.IN0
AIN[4] => Mux~18.IN0
AIN[5] => Mux~17.IN0
AIN[6] => Mux~16.IN0
AIN[7] => Mux~15.IN0
DATASOUT[0] <= data[0].DB_MAX_OUTPUT_PORT_TYPE
DATASOUT[1] <= data[1].DB_MAX_OUTPUT_PORT_TYPE
DATASOUT[2] <= data[2].DB_MAX_OUTPUT_PORT_TYPE
DATASOUT[3] <= data[3].DB_MAX_OUTPUT_PORT_TYPE
DATASOUT[4] <= data[4].DB_MAX_OUTPUT_PORT_TYPE
DATASOUT[5] <= data[5].DB_MAX_OUTPUT_PORT_TYPE
DATASOUT[6] <= data[6].DB_MAX_OUTPUT_PORT_TYPE
DATASOUT[7] <= data[7].DB_MAX_OUTPUT_PORT_TYPE
ADDOUT[0] <= cnt2[0].DB_MAX_OUTPUT_PORT_TYPE
ADDOUT[1] <= cnt2[1].DB_MAX_OUTPUT_PORT_TYPE
ADDOUT[2] <= cnt2[2].DB_MAX_OUTPUT_PORT_TYPE
ADDOUT[3] <= cnt2[3].DB_MAX_OUTPUT_PORT_TYPE
ADDOUT[4] <= cnt2[4].DB_MAX_OUTPUT_PORT_TYPE
ADDOUT[5] <= cnt2[5].DB_MAX_OUTPUT_PORT_TYPE
ADDOUT[6] <= cnt2[6].DB_MAX_OUTPUT_PORT_TYPE
ADDOUT[7] <= cnt2[7].DB_MAX_OUTPUT_PORT_TYPE
ADDOUT[8] <= cnt2[8].DB_MAX_OUTPUT_PORT_TYPE
ADDOUT[9] <= cnt2[9].DB_MAX_OUTPUT_PORT_TYPE
ADDOUT[10] <= cnt2[10].DB_MAX_OUTPUT_PORT_TYPE
WRS1 <= WR.DB_MAX_OUTPUT_PORT_TYPE


|TEST|CONV_SINGLE:inst5
SINGLE => process0~0.IN1
ADDATA[0] => LessThan~0.IN8
ADDATA[1] => LessThan~0.IN7
ADDATA[2] => LessThan~0.IN6
ADDATA[3] => LessThan~0.IN5
ADDATA[4] => LessThan~0.IN4
ADDATA[5] => LessThan~0.IN3
ADDATA[6] => LessThan~0.IN2
ADDATA[7] => LessThan~0.IN1
V0LTAGE_TRI[0] => LessThan~0.IN16
V0LTAGE_TRI[1] => LessThan~0.IN15
V0LTAGE_TRI[2] => LessThan~0.IN14
V0LTAGE_TRI[3] => LessThan~0.IN13
V0LTAGE_TRI[4] => LessThan~0.IN12
V0LTAGE_TRI[5] => LessThan~0.IN11
V0LTAGE_TRI[6] => LessThan~0.IN10
V0LTAGE_TRI[7] => LessThan~0.IN9
EN <= process0~0.DB_MAX_OUTPUT_PORT_TYPE


|TEST|BUS_1:inst9
P0I[0] => Select~7.IN1
P0I[0] => Select~16.IN1
P0I[0] => Select~24.IN1
P0I[0] => Select~25.IN1
P0I[0] => Select~33.IN1
P0I[0] => Select~34.IN1
P0I[0] => Select~42.IN1
P0I[0] => Select~50.IN1
P0I[0] => Select~58.IN1
P0I[0] => LATCH_ADDRES[0].DATAIN
P0I[1] => Select~6.IN1
P0I[1] => Select~15.IN1
P0I[1] => Select~23.IN1
P0I[1] => Select~32.IN1
P0I[1] => Select~41.IN1
P0I[1] => Select~49.IN1
P0I[1] => Select~57.IN1
P0I[1] => LATCH_ADDRES[1].DATAIN
P0I[2] => Select~5.IN1
P0I[2] => Select~14.IN1
P0I[2] => Select~22.IN1
P0I[2] => Select~31.IN1
P0I[2] => Select~40.IN1
P0I[2] => Select~48.IN1
P0I[2] => Select~56.IN1
P0I[2] => LATCH_ADDRES[2].DATAIN
P0I[3] => Select~4.IN1
P0I[3] => Select~13.IN1
P0I[3] => Select~21.IN1
P0I[3] => Select~30.IN1
P0I[3] => Select~39.IN1
P0I[3] => Select~47.IN1
P0I[3] => Select~55.IN1
P0I[3] => LATCH_ADDRES[3].DATAIN
P0I[4] => Select~3.IN1
P0I[4] => Select~12.IN1
P0I[4] => Select~20.IN1
P0I[4] => Select~29.IN1
P0I[4] => Select~38.IN1
P0I[4] => Select~46.IN1
P0I[4] => Select~54.IN1
P0I[4] => LATCH_ADDRES[4].DATAIN
P0I[5] => Select~2.IN1
P0I[5] => Select~11.IN1
P0I[5] => Select~19.IN1
P0I[5] => Select~28.IN1
P0I[5] => Select~37.IN1
P0I[5] => Select~45.IN1
P0I[5] => Select~53.IN1
P0I[5] => LATCH_ADDRES[5].DATAIN
P0I[6] => Select~1.IN1
P0I[6] => Select~10.IN1
P0I[6] => Select~18.IN1
P0I[6] => Select~27.IN1
P0I[6] => Select~36.IN1
P0I[6] => Select~44.IN1
P0I[6] => Select~52.IN1
P0I[6] => LATCH_ADDRES[6].DATAIN
P0I[7] => Select~0.IN1
P0I[7] => Select~9.IN1
P0I[7] => Select~17.IN1
P0I[7] => Select~26.IN1
P0I[7] => Select~35.IN1
P0I[7] => Select~43.IN1
P0I[7] => Select~51.IN1
P0I[7] => LATCH_ADDRES[7].DATAIN
P0T[0] <= P0_OUT[0].DB_MAX_OUTPUT_PORT_TYPE
P0T[1] <= P0_OUT[1].DB_MAX_OUTPUT_PORT_TYPE
P0T[2] <= P0_OUT[2].DB_MAX_OUTPUT_PORT_TYPE
P0T[3] <= P0_OUT[3].DB_MAX_OUTPUT_PORT_TYPE
P0T[4] <= P0_OUT[4].DB_MAX_OUTPUT_PORT_TYPE
P0T[5] <= P0_OUT[5].DB_MAX_OUTPUT_PORT_TYPE
P0T[6] <= P0_OUT[6].DB_MAX_OUTPUT_PORT_TYPE
P0T[7] <= P0_OUT[7].DB_MAX_OUTPUT_PORT_TYPE
ALE => LATCH_ADDRES[6].CLK
ALE => LATCH_ADDRES[5].CLK
ALE => LATCH_ADDRES[4].CLK
ALE => LATCH_ADDRES[3].CLK
ALE => LATCH_ADDRES[2].CLK
ALE => LATCH_ADDRES[1].CLK
ALE => LATCH_ADDRES[0].CLK
ALE => LATCH_ADDRES[7].CLK
RD => process1~0.IN0
WR => process2~0.IN1
CLK => P0_OUT[7].CLK
CLK => P0_OUT[6].CLK
CLK => P0_OUT[5].CLK
CLK => P0_OUT[4].CLK
CLK => P0_OUT[3].CLK
CLK => P0_OUT[2].CLK
CLK => P0_OUT[1].CLK
CLK => P0_OUT[0].CLK
CLK => GX~reg0.CLK
CLK => RAMTMP0[6].CLK
CLK => RAMTMP0[5].CLK
CLK => RAMTMP0[4].CLK
CLK => RAMTMP0[3].CLK
CLK => RAMTMP0[2].CLK
CLK => RAMTMP0[1].CLK
CLK => RAMTMP0[0].CLK
CLK => TMP.CLK
CLK => RAMTMP1[7].CLK
CLK => RAMTMP1[6].CLK
CLK => RAMTMP1[5].CLK
CLK => RAMTMP1[4].CLK
CLK => RAMTMP1[3].CLK
CLK => RAMTMP1[2].CLK