mux_2de.tdf

数字示波器的FPGA实现 VHDL编写 Quartus7.1测试通过

--lpm_mux CASCADE_CHAIN="MANUAL" DEVICE_FAMILY="Cyclone" IGNORE_CASCADE_BUFFERS="OFF" LPM_PIPELINE=1 LPM_SIZE=2 LPM_WIDTH=8 LPM_WIDTHS=1 clock data result sel
--VERSION_BEGIN 4.1 cbx_lpm_mux 2004:03:10:10:50:34:SJ cbx_mgl 2004:06:17:17:30:06:SJ  VERSION_END


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--  Any  megafunction  design,  and related netlist (encrypted  or  decrypted),
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--  to program  PLD  devices (but not masked  PLD  devices) from  Altera.   Any
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--synthesis_resources = lut 8 
SUBDESIGN mux_2de
( 
	clock	:	input;
	data[15..0]	:	input;
	result[7..0]	:	output;
	sel[0..0]	:	input;
) 
VARIABLE 
	external_latency_ffsa[7..0] : dffe;
	result_node[7..0]	: WIRE;
	sel_node[0..0]	: WIRE;
	w4w	: WIRE;
	w_data19w[1..0]	: WIRE;
	w_data31w[1..0]	: WIRE;
	w_data43w[1..0]	: WIRE;
	w_data55w[1..0]	: WIRE;
	w_data5w[1..0]	: WIRE;
	w_data67w[1..0]	: WIRE;
	w_data79w[1..0]	: WIRE;
	w_data91w[1..0]	: WIRE;
	w_result12w	: WIRE;
	w_result20w	: WIRE;
	w_result26w	: WIRE;
	w_result32w	: WIRE;
	w_result38w	: WIRE;
	w_result44w	: WIRE;
	w_result50w	: WIRE;
	w_result56w	: WIRE;
	w_result62w	: WIRE;
	w_result68w	: WIRE;
	w_result6w	: WIRE;
	w_result74w	: WIRE;
	w_result80w	: WIRE;
	w_result86w	: WIRE;
	w_result92w	: WIRE;
	w_result98w	: WIRE;

BEGIN 
	external_latency_ffsa[].CLK = clock;
	external_latency_ffsa[].D = ( result_node[]);
	result[7..0] = external_latency_ffsa[7..0].Q;
	result_node[] = ( w_result92w, w_result80w, w_result68w, w_result56w, w_result44w, w_result32w, w_result20w, w_result6w);
	sel_node[] = ( sel[0..0]);
	w4w = clock;
	w_data19w[] = ( data[9..9], data[1..1]);
	w_data31w[] = ( data[10..10], data[2..2]);
	w_data43w[] = ( data[11..11], data[3..3]);
	w_data55w[] = ( data[12..12], data[4..4]);
	w_data5w[] = ( data[8..8], data[0..0]);
	w_data67w[] = ( data[13..13], data[5..5]);
	w_data79w[] = ( data[14..14], data[6..6]);
	w_data91w[] = ( data[15..15], data[7..7]);
	w_result12w = ((sel_node[] & w_data5w[1..1]) # ((! sel_node[]) & w_data5w[0..0]));
	w_result20w = w_result26w;
	w_result26w = ((sel_node[] & w_data19w[1..1]) # ((! sel_node[]) & w_data19w[0..0]));
	w_result32w = w_result38w;
	w_result38w = ((sel_node[] & w_data31w[1..1]) # ((! sel_node[]) & w_data31w[0..0]));
	w_result44w = w_result50w;
	w_result50w = ((sel_node[] & w_data43w[1..1]) # ((! sel_node[]) & w_data43w[0..0]));
	w_result56w = w_result62w;
	w_result62w = ((sel_node[] & w_data55w[1..1]) # ((! sel_node[]) & w_data55w[0..0]));
	w_result68w = w_result74w;
	w_result6w = w_result12w;
	w_result74w = ((sel_node[] & w_data67w[1..1]) # ((! sel_node[]) & w_data67w[0..0]));
	w_result80w = w_result86w;
	w_result86w = ((sel_node[] & w_data79w[1..1]) # ((! sel_node[]) & w_data79w[0..0]));
	w_result92w = w_result98w;
	w_result98w = ((sel_node[] & w_data91w[1..1]) # ((! sel_node[]) & w_data91w[0..0]));
END;
--VALID FILE