test.tan.qmsg

数字示波器的FPGA实现 VHDL编写 Quartus7.1测试通过

{ "Info" "ITDB_TH_RESULT" "BUS_1:inst9\|RAMTMP0\[3\] P0\[3\] CLK -4.023 ns register " "Info: th for register BUS_1:inst9\|RAMTMP0\[3\] (data pin = P0\[3\], clock pin = CLK) is -4.023 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK destination 2.759 ns + Longest register " "Info: + Longest clock path from clock CLK to destination register is 2.759 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns CLK 1 CLK PIN_17 213 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_17; Fanout = 213; CLK Node = 'CLK'" {  } { { "e:/ywh/quartusii/scanwave/db/TEST_cmp.qrpt" "" "" { Report "e:/ywh/quartusii/scanwave/db/TEST_cmp.qrpt" Compiler "TEST" "UNKNOWN" "V1" "e:/ywh/quartusii/scanwave/db/TEST.quartus_db" { Floorplan "" "" "" { CLK } "NODE_NAME" } } } { "e:/ywh/quartusii/scanwave/test.bdf" "" "" { Schematic "e:/ywh/quartusii/scanwave/test.bdf" { { 512 32 200 528 "CLK" "" } { 336 280 312 352 "CLK" "" } { 352 960 984 368 "CLK" "" } { 368 960 984 384 "CLK" "" } { 504 200 264 520 "CLK" "" } { 272 616 656 288 "CLK" "" } { 816 200 240 832 "CLK" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.579 ns) + CELL(0.711 ns) 2.759 ns BUS_1:inst9\|RAMTMP0\[3\] 2 REG LC_X23_Y7_N8 2 " "Info: 2: + IC(0.579 ns) + CELL(0.711 ns) = 2.759 ns; Loc. = LC_X23_Y7_N8; Fanout = 2; REG Node = 'BUS_1:inst9\|RAMTMP0\[3\]'" {  } { { "e:/ywh/quartusii/scanwave/db/TEST_cmp.qrpt" "" "" { Report "e:/ywh/quartusii/scanwave/db/TEST_cmp.qrpt" Compiler "TEST" "UNKNOWN" "V1" "e:/ywh/quartusii/scanwave/db/TEST.quartus_db" { Floorplan "" "" "1.290 ns" { CLK BUS_1:inst9|RAMTMP0[3] } "NODE_NAME" } } } { "e:/ywh/quartusii/scanwave/BUS_1.vhd" "" "" { Text "e:/ywh/quartusii/scanwave/BUS_1.vhd" 56 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns 79.01 % " "Info: Total cell delay = 2.180 ns ( 79.01 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.579 ns 20.99 % " "Info: Total interconnect delay = 0.579 ns ( 20.99 % )" {  } {  } 0}  } { { "e:/ywh/quartusii/scanwave/db/TEST_cmp.qrpt" "" "" { Report "e:/ywh/quartusii/scanwave/db/TEST_cmp.qrpt" Compiler "TEST" "UNKNOWN" "V1" "e:/ywh/quartusii/scanwave/db/TEST.quartus_db" { Floorplan "" "" "2.759 ns" { CLK BUS_1:inst9|RAMTMP0[3] } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_TH_DELAY" "0.015 ns + " "Info: + Micro hold delay of destination is 0.015 ns" {  } { { "e:/ywh/quartusii/scanwave/BUS_1.vhd" "" "" { Text "e:/ywh/quartusii/scanwave/BUS_1.vhd" 56 -1 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.797 ns - Shortest pin register " "Info: - Shortest pin to register delay is 6.797 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns P0\[3\] 1 PIN PIN_85 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PIN_85; Fanout = 1; PIN Node = 'P0\[3\]'" {  } { { "e:/ywh/quartusii/scanwave/db/TEST_cmp.qrpt" "" "" { Report "e:/ywh/quartusii/scanwave/db/TEST_cmp.qrpt" Compiler "TEST" "UNKNOWN" "V1" "e:/ywh/quartusii/scanwave/db/TEST.quartus_db" { Floorplan "" "" "" { P0[3] } "NODE_NAME" } } } { "e:/ywh/quartusii/scanwave/test.bdf" "" "" { Schematic "e:/ywh/quartusii/scanwave/test.bdf" { { 640 32 208 656 "P0\[7..0\]" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns P0~4 2 COMB IOC_X27_Y7_N1 9 " "Info: 2: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = IOC_X27_Y7_N1; Fanout = 9; COMB Node = 'P0~4'" {  } { { "e:/ywh/quartusii/scanwave/db/TEST_cmp.qrpt" "" "" { Report "e:/ywh/quartusii/scanwave/db/TEST_cmp.qrpt" Compiler "TEST" "UNKNOWN" "V1" "e:/ywh/quartusii/scanwave/db/TEST.quartus_db" { Floorplan "" "" "1.469 ns" { P0[3] P0~4 } "NODE_NAME" } } } { "e:/ywh/quartusii/scanwave/test.bdf" "" "" { Schematic "e:/ywh/quartusii/scanwave/test.bdf" { { 640 32 208 656 "P0\[7..0\]" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(5.019 ns) + CELL(0.309 ns) 6.797 ns BUS_1:inst9\|RAMTMP0\[3\] 3 REG LC_X23_Y7_N8 2 " "Info: 3: + IC(5.019 ns) + CELL(0.309 ns) = 6.797 ns; Loc. = LC_X23_Y7_N8; Fanout = 2; REG Node = 'BUS_1:inst9\|RAMTMP0\[3\]'" {  } { { "e:/ywh/quartusii/scanwave/db/TEST_cmp.qrpt" "" "" { Report "e:/ywh/quartusii/scanwave/db/TEST_cmp.qrpt" Compiler "TEST" "UNKNOWN" "V1" "e:/ywh/quartusii/scanwave/db/TEST.quartus_db" { Floorplan "" "" "5.328 ns" { P0~4 BUS_1:inst9|RAMTMP0[3] } "NODE_NAME" } } } { "e:/ywh/quartusii/scanwave/BUS_1.vhd" "" "" { Text "e:/ywh/quartusii/scanwave/BUS_1.vhd" 56 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.778 ns 26.16 % " "Info: Total cell delay = 1.778 ns ( 26.16 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.019 ns 73.84 % " "Info: Total interconnect delay = 5.019 ns ( 73.84 % )" {  } {  } 0}  } { { "e:/ywh/quartusii/scanwave/db/TEST_cmp.qrpt" "" "" { Report "e:/ywh/quartusii/scanwave/db/TEST_cmp.qrpt" Compiler "TEST" "UNKNOWN" "V1" "e:/ywh/quartusii/scanwave/db/TEST.quartus_db" { Floorplan "" "" "6.797 ns" { P0[3] P0~4 BUS_1:inst9|RAMTMP0[3] } "NODE_NAME" } } }  } 0}  } { { "e:/ywh/quartusii/scanwave/db/TEST_cmp.qrpt" "" "" { Report "e:/ywh/quartusii/scanwave/db/TEST_cmp.qrpt" Compiler "TEST" "UNKNOWN" "V1" "e:/ywh/quartusii/scanwave/db/TEST.quartus_db" { Floorplan "" "" "2.759 ns" { CLK BUS_1:inst9|RAMTMP0[3] } "NODE_NAME" } } } { "e:/ywh/quartusii/scanwave/db/TEST_cmp.qrpt" "" "" { Report "e:/ywh/quartusii/scanwave/db/TEST_cmp.qrpt" Compiler "TEST" "UNKNOWN" "V1" "e:/ywh/quartusii/scanwave/db/TEST.quartus_db" { Floorplan "" "" "6.797 ns" { P0[3] P0~4 BUS_1:inst9|RAMTMP0[3] } "NODE_NAME" } } }  } 0}
{ "Info" "ITDB_FULL_MIN_TCO_RESULT" "CLK P0\[1\] BUS_1:inst9\|P0_OUT\[1\] 6.566 ns register " "Info: Minimum tco from clock CLK to destination pin P0\[1\] through register BUS_1:inst9\|P0_OUT\[1\] is 6.566 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK source 2.759 ns + Shortest register " "Info: + Shortest clock path from clock CLK to source register is 2.759 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns CLK 1 CLK PIN_17 213 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_17; Fanout = 213; CLK Node = 'CLK'" {  } { { "e:/ywh/quartusii/scanwave/db/TEST_cmp.qrpt" "" "" { Report "e:/ywh/quartusii/scanwave/db/TEST_cmp.qrpt" Compiler "TEST" "UNKNOWN" "V1" "e:/ywh/quartusii/scanwave/db/TEST.quartus_db" { Floorplan "" "" "" { CLK } "NODE_NAME" } } } { "e:/ywh/quartusii/scanwave/test.bdf" "" "" { Schematic "e:/ywh/quartusii/scanwave/test.bdf" { { 512 32 200 528 "CLK" "" } { 336 280 312 352 "CLK" "" } { 352 960 984 368 "CLK" "" } { 368 960 984 384 "CLK" "" } { 504 200 264 520 "CLK" "" } { 272 616 656 288 "CLK" "" } { 816 200 240 832 "CLK" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.579 ns) + CELL(0.711 ns) 2.759 ns BUS_1:inst9\|P0_OUT\[1\] 2 REG LC_X23_Y9_N8 2 " "Info: 2: + IC(0.579 ns) + CELL(0.711 ns) = 2.759 ns; Loc. = LC_X23_Y9_N8; Fanout = 2; REG Node = 'BUS_1:inst9\|P0_OUT\[1\]'" {  } { { "e:/ywh/quartusii/scanwave/db/TEST_cmp.qrpt" "" "" { Report "e:/ywh/quartusii/scanwave/db/TEST_cmp.qrpt" Compiler "TEST" "UNKNOWN" "V1" "e:/ywh/quartusii/scanwave/db/TEST.quartus_db" { Floorplan "" "" "1.290 ns" { CLK BUS_1:inst9|P0_OUT[1] } "NODE_NAME" } } } { "e:/ywh/quartusii/scanwave/BUS_1.vhd" "" "" { Text "e:/ywh/quartusii/scanwave/BUS_1.vhd" 38 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns 79.01 % " "Info: Total cell delay = 2.180 ns ( 79.01 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.579 ns 20.99 % " "Info: Total interconnect delay = 0.579 ns ( 20.99 % )" {  } {  } 0}  } { { "e:/ywh/quartusii/scanwave/db/TEST_cmp.qrpt" "" "" { Report "e:/ywh/quartusii/scanwave/db/TEST_cmp.qrpt" Compiler "TEST" "UNKNOWN" "V1" "e:/ywh/quartusii/scanwave/db/TEST.quartus_db" { Floorplan "" "" "2.759 ns" { CLK BUS_1:inst9|P0_OUT[1] } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "e:/ywh/quartusii/scanwave/BUS_1.vhd" "" "" { Text "e:/ywh/quartusii/scanwave/BUS_1.vhd" 38 -1 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.583 ns + Shortest register pin " "Info: + Shortest register to pin delay is 3.583 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns BUS_1:inst9\|P0_OUT\[1\] 1 REG LC_X23_Y9_N8 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X23_Y9_N8; Fanout = 2; REG Node = 'BUS_1:inst9\|P0_OUT\[1\]'" {  } { { "e:/ywh/quartusii/scanwave/db/TEST_cmp.qrpt" "" "" { Report "e:/ywh/quartusii/scanwave/db/TEST_cmp.qrpt" Compiler "TEST" "UNKNOWN" "V1" "e:/ywh/quartusii/scanwave/db/TEST.quartus_db" { Floorplan "" "" "" { BUS_1:inst9|P0_OUT[1] } "NODE_NAME" } } } { "e:/ywh/quartusii/scanwave/BUS_1.vhd" "" "" { Text "e:/ywh/quartusii/scanwave/BUS_1.vhd" 38 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.459 ns) + CELL(2.124 ns) 3.583 ns P0\[1\] 2 PIN PIN_97 0 " "Info: 2: + IC(1.459 ns) + CELL(2.124 ns) = 3.583 ns; Loc. = PIN_97; Fanout = 0; PIN Node = 'P0\[1\]'" {  } { { "e:/ywh/quartusii/scanwave/db/TEST_cmp.qrpt" "" "" { Report "e:/ywh/quartusii/scanwave/db/TEST_cmp.qrpt" Compiler "TEST" "UNKNOWN" "V1" "e:/ywh/quartusii/scanwave/db/TEST.quartus_db" { Floorplan "" "" "3.583 ns" { BUS_1:inst9|P0_OUT[1] P0[1] } "NODE_NAME" } } } { "e:/ywh/quartusii/scanwave/test.bdf" "" "" { Schematic "e:/ywh/quartusii/scanwave/test.bdf" { { 640 32 208 656 "P0\[7..0\]" "" } } } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.124 ns 59.28 % " "Info: Total cell delay = 2.124 ns ( 59.28 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.459 ns 40.72 % " "Info: Total interconnect delay = 1.459 ns ( 40.72 % )" {  } {  } 0}  } { { "e:/ywh/quartusii/scanwave/db/TEST_cmp.qrpt" "" "" { Report "e:/ywh/quartusii/scanwave/db/TEST_cmp.qrpt" Compiler "TEST" "UNKNOWN" "V1" "e:/ywh/quartusii/scanwave/db/TEST.quartus_db" { Floorplan "" "" "3.583 ns" { BUS_1:inst9|P0_OUT[1] P0[1] } "NODE_NAME" } } }  } 0}  } { { "e:/ywh/quartusii/scanwave/db/TEST_cmp.qrpt" "" "" { Report "e:/ywh/quartusii/scanwave/db/TEST_cmp.qrpt" Compiler "TEST" "UNKNOWN" "V1" "e:/ywh/quartusii/scanwave/db/TEST.quartus_db" { Floorplan "" "" "2.759 ns" { CLK BUS_1:inst9|P0_OUT[1] } "NODE_NAME" } } } { "e:/ywh/quartusii/scanwave/db/TEST_cmp.qrpt" "" "" { Report "e:/ywh/quartusii/scanwave/db/TEST_cmp.qrpt" Compiler "TEST" "UNKNOWN" "V1" "e:/ywh/quartusii/scanwave/db/TEST.quartus_db" { Floorplan "" "" "3.583 ns" { BUS_1:inst9|P0_OUT[1] P0[1] } "NODE_NAME" } } }  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 12 s " "Info: Quartus II Timing Analyzer was successful. 0 errors, 12 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Wed Aug 10 09:45:06 2005 " "Info: Processing ended: Wed Aug 10 09:45:06 2005" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:00 " "Info: Elapsed time: 00:00:00" {  } {  } 0}  } {  } 0}