test.tan.qmsg

数字示波器的FPGA实现 VHDL编写 Quartus7.1测试通过

{ "Warning" "WTAN_CLOCK_WILL_NOT_OPERATE" "CLK 158 " "Warning: Circuit may not operate. Detected 158 non-operational path(s) clocked by clock CLK with clock skew larger than data delay. See Compilation Report for details." {  } {  } 0}
{ "Info" "ITDB_FULL_NEGATIVE_HOLD_RESULT" "BUS_1:inst9\|RAMTMP2\[1\] VOLTAGE_CONV:inst4\|TEMP\[1\] CLK 4.309 ns " "Info: Found hold time violation between source  pin or register BUS_1:inst9\|RAMTMP2\[1\] and destination pin or register VOLTAGE_CONV:inst4\|TEMP\[1\] for clock CLK (Hold time is 4.309 ns)" { { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "5.651 ns + Largest " "Info: + Largest clock skew is 5.651 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK destination 8.410 ns + Longest register " "Info: + Longest clock path from clock CLK to destination register is 8.410 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns CLK 1 CLK PIN_17 213 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_17; Fanout = 213; CLK Node = 'CLK'" {  } { { "e:/ywh/quartusii/scanwave/db/TEST_cmp.qrpt" "" "" { Report "e:/ywh/quartusii/scanwave/db/TEST_cmp.qrpt" Compiler "TEST" "UNKNOWN" "V1" "e:/ywh/quartusii/scanwave/db/TEST.quartus_db" { Floorplan "" "" "" { CLK } "NODE_NAME" } } } { "e:/ywh/quartusii/scanwave/test.bdf" "" "" { Schematic "e:/ywh/quartusii/scanwave/test.bdf" { { 512 32 200 528 "CLK" "" } { 336 280 312 352 "CLK" "" } { 352 960 984 368 "CLK" "" } { 368 960 984 384 "CLK" "" } { 504 200 264 520 "CLK" "" } { 272 616 656 288 "CLK" "" } { 816 200 240 832 "CLK" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.541 ns) + CELL(0.935 ns) 2.945 ns AD_SRAM:inst2\|WR 2 REG LC_X21_Y4_N7 12 " "Info: 2: + IC(0.541 ns) + CELL(0.935 ns) = 2.945 ns; Loc. = LC_X21_Y4_N7; Fanout = 12; REG Node = 'AD_SRAM:inst2\|WR'" {  } { { "e:/ywh/quartusii/scanwave/db/TEST_cmp.qrpt" "" "" { Report "e:/ywh/quartusii/scanwave/db/TEST_cmp.qrpt" Compiler "TEST" "UNKNOWN" "V1" "e:/ywh/quartusii/scanwave/db/TEST.quartus_db" { Floorplan "" "" "1.476 ns" { CLK AD_SRAM:inst2|WR } "NODE_NAME" } } } { "E:/ywh/QUARTUSII/scanwave/AD_SRAM.vhd" "" "" { Text "E:/ywh/QUARTUSII/scanwave/AD_SRAM.vhd" 24 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(4.754 ns) + CELL(0.711 ns) 8.410 ns VOLTAGE_CONV:inst4\|TEMP\[1\] 3 REG LC_X16_Y6_N1 1 " "Info: 3: + IC(4.754 ns) + CELL(0.711 ns) = 8.410 ns; Loc. = LC_X16_Y6_N1; Fanout = 1; REG Node = 'VOLTAGE_CONV:inst4\|TEMP\[1\]'" {  } { { "e:/ywh/quartusii/scanwave/db/TEST_cmp.qrpt" "" "" { Report "e:/ywh/quartusii/scanwave/db/TEST_cmp.qrpt" Compiler "TEST" "UNKNOWN" "V1" "e:/ywh/quartusii/scanwave/db/TEST.quartus_db" { Floorplan "" "" "5.465 ns" { AD_SRAM:inst2|WR VOLTAGE_CONV:inst4|TEMP[1] } "NODE_NAME" } } } { "E:/ywh/QUARTUSII/scanwave/VOLTAGE_CONV.vhd" "" "" { Text "E:/ywh/QUARTUSII/scanwave/VOLTAGE_CONV.vhd" 35 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.115 ns 37.04 % " "Info: Total cell delay = 3.115 ns ( 37.04 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.295 ns 62.96 % " "Info: Total interconnect delay = 5.295 ns ( 62.96 % )" {  } {  } 0}  } { { "e:/ywh/quartusii/scanwave/db/TEST_cmp.qrpt" "" "" { Report "e:/ywh/quartusii/scanwave/db/TEST_cmp.qrpt" Compiler "TEST" "UNKNOWN" "V1" "e:/ywh/quartusii/scanwave/db/TEST.quartus_db" { Floorplan "" "" "8.410 ns" { CLK AD_SRAM:inst2|WR VOLTAGE_CONV:inst4|TEMP[1] } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK source 2.759 ns - Shortest register " "Info: - Shortest clock path from clock CLK to source register is 2.759 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns CLK 1 CLK PIN_17 213 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_17; Fanout = 213; CLK Node = 'CLK'" {  } { { "e:/ywh/quartusii/scanwave/db/TEST_cmp.qrpt" "" "" { Report "e:/ywh/quartusii/scanwave/db/TEST_cmp.qrpt" Compiler "TEST" "UNKNOWN" "V1" "e:/ywh/quartusii/scanwave/db/TEST.quartus_db" { Floorplan "" "" "" { CLK } "NODE_NAME" } } } { "e:/ywh/quartusii/scanwave/test.bdf" "" "" { Schematic "e:/ywh/quartusii/scanwave/test.bdf" { { 512 32 200 528 "CLK" "" } { 336 280 312 352 "CLK" "" } { 352 960 984 368 "CLK" "" } { 368 960 984 384 "CLK" "" } { 504 200 264 520 "CLK" "" } { 272 616 656 288 "CLK" "" } { 816 200 240 832 "CLK" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.579 ns) + CELL(0.711 ns) 2.759 ns BUS_1:inst9\|RAMTMP2\[1\] 2 REG LC_X16_Y6_N8 4 " "Info: 2: + IC(0.579 ns) + CELL(0.711 ns) = 2.759 ns; Loc. = LC_X16_Y6_N8; Fanout = 4; REG Node = 'BUS_1:inst9\|RAMTMP2\[1\]'" {  } { { "e:/ywh/quartusii/scanwave/db/TEST_cmp.qrpt" "" "" { Report "e:/ywh/quartusii/scanwave/db/TEST_cmp.qrpt" Compiler "TEST" "UNKNOWN" "V1" "e:/ywh/quartusii/scanwave/db/TEST.quartus_db" { Floorplan "" "" "1.290 ns" { CLK BUS_1:inst9|RAMTMP2[1] } "NODE_NAME" } } } { "e:/ywh/quartusii/scanwave/BUS_1.vhd" "" "" { Text "e:/ywh/quartusii/scanwave/BUS_1.vhd" 56 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns 79.01 % " "Info: Total cell delay = 2.180 ns ( 79.01 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.579 ns 20.99 % " "Info: Total interconnect delay = 0.579 ns ( 20.99 % )" {  } {  } 0}  } { { "e:/ywh/quartusii/scanwave/db/TEST_cmp.qrpt" "" "" { Report "e:/ywh/quartusii/scanwave/db/TEST_cmp.qrpt" Compiler "TEST" "UNKNOWN" "V1" "e:/ywh/quartusii/scanwave/db/TEST.quartus_db" { Floorplan "" "" "2.759 ns" { CLK BUS_1:inst9|RAMTMP2[1] } "NODE_NAME" } } }  } 0}  } { { "e:/ywh/quartusii/scanwave/db/TEST_cmp.qrpt" "" "" { Report "e:/ywh/quartusii/scanwave/db/TEST_cmp.qrpt" Compiler "TEST" "UNKNOWN" "V1" "e:/ywh/quartusii/scanwave/db/TEST.quartus_db" { Floorplan "" "" "8.410 ns" { CLK AD_SRAM:inst2|WR VOLTAGE_CONV:inst4|TEMP[1] } "NODE_NAME" } } } { "e:/ywh/quartusii/scanwave/db/TEST_cmp.qrpt" "" "" { Report "e:/ywh/quartusii/scanwave/db/TEST_cmp.qrpt" Compiler "TEST" "UNKNOWN" "V1" "e:/ywh/quartusii/scanwave/db/TEST.quartus_db" { Floorplan "" "" "2.759 ns" { CLK BUS_1:inst9|RAMTMP2[1] } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns - " "Info: - Micro clock to output delay of source is 0.224 ns" {  } { { "e:/ywh/quartusii/scanwave/BUS_1.vhd" "" "" { Text "e:/ywh/quartusii/scanwave/BUS_1.vhd" 56 -1 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "1.133 ns - Shortest register register " "Info: - Shortest register to register delay is 1.133 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns BUS_1:inst9\|RAMTMP2\[1\] 1 REG LC_X16_Y6_N8 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X16_Y6_N8; Fanout = 4; REG Node = 'BUS_1:inst9\|RAMTMP2\[1\]'" {  } { { "e:/ywh/quartusii/scanwave/db/TEST_cmp.qrpt" "" "" { Report "e:/ywh/quartusii/scanwave/db/TEST_cmp.qrpt" Compiler "TEST" "UNKNOWN" "V1" "e:/ywh/quartusii/scanwave/db/TEST.quartus_db" { Floorplan "" "" "" { BUS_1:inst9|RAMTMP2[1] } "NODE_NAME" } } } { "e:/ywh/quartusii/scanwave/BUS_1.vhd" "" "" { Text "e:/ywh/quartusii/scanwave/BUS_1.vhd" 56 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.526 ns) + CELL(0.607 ns) 1.133 ns VOLTAGE_CONV:inst4\|TEMP\[1\] 2 REG LC_X16_Y6_N1 1 " "Info: 2: + IC(0.526 ns) + CELL(0.607 ns) = 1.133 ns; Loc. = LC_X16_Y6_N1; Fanout = 1; REG Node = 'VOLTAGE_CONV:inst4\|TEMP\[1\]'" {  } { { "e:/ywh/quartusii/scanwave/db/TEST_cmp.qrpt" "" "" { Report "e:/ywh/quartusii/scanwave/db/TEST_cmp.qrpt" Compiler "TEST" "UNKNOWN" "V1" "e:/ywh/quartusii/scanwave/db/TEST.quartus_db" { Floorplan "" "" "1.133 ns" { BUS_1:inst9|RAMTMP2[1] VOLTAGE_CONV:inst4|TEMP[1] } "NODE_NAME" } } } { "E:/ywh/QUARTUSII/scanwave/VOLTAGE_CONV.vhd" "" "" { Text "E:/ywh/QUARTUSII/scanwave/VOLTAGE_CONV.vhd" 35 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.607 ns 53.57 % " "Info: Total cell delay = 0.607 ns ( 53.57 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.526 ns 46.43 % " "Info: Total interconnect delay = 0.526 ns ( 46.43 % )" {  } {  } 0}  } { { "e:/ywh/quartusii/scanwave/db/TEST_cmp.qrpt" "" "" { Report "e:/ywh/quartusii/scanwave/db/TEST_cmp.qrpt" Compiler "TEST" "UNKNOWN" "V1" "e:/ywh/quartusii/scanwave/db/TEST.quartus_db" { Floorplan "" "" "1.133 ns" { BUS_1:inst9|RAMTMP2[1] VOLTAGE_CONV:inst4|TEMP[1] } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_TH_DELAY" "0.015 ns + " "Info: + Micro hold delay of destination is 0.015 ns" {  } { { "E:/ywh/QUARTUSII/scanwave/VOLTAGE_CONV.vhd" "" "" { Text "E:/ywh/QUARTUSII/scanwave/VOLTAGE_CONV.vhd" 35 -1 0 } }  } 0}  } { { "e:/ywh/quartusii/scanwave/db/TEST_cmp.qrpt" "" "" { Report "e:/ywh/quartusii/scanwave/db/TEST_cmp.qrpt" Compiler "TEST" "UNKNOWN" "V1" "e:/ywh/quartusii/scanwave/db/TEST.quartus_db" { Floorplan "" "" "8.410 ns" { CLK AD_SRAM:inst2|WR VOLTAGE_CONV:inst4|TEMP[1] } "NODE_NAME" } } } { "e:/ywh/quartusii/scanwave/db/TEST_cmp.qrpt" "" "" { Report "e:/ywh/quartusii/scanwave/db/TEST_cmp.qrpt" Compiler "TEST" "UNKNOWN" "V1" "e:/ywh/quartusii/scanwave/db/TEST.quartus_db" { Floorplan "" "" "2.759 ns" { CLK BUS_1:inst9|RAMTMP2[1] } "NODE_NAME" } } } { "e:/ywh/quartusii/scanwave/db/TEST_cmp.qrpt" "" "" { Report "e:/ywh/quartusii/scanwave/db/TEST_cmp.qrpt" Compiler "TEST" "UNKNOWN" "V1" "e:/ywh/quartusii/scanwave/db/TEST.quartus_db" { Floorplan "" "" "1.133 ns" { BUS_1:inst9|RAMTMP2[1] VOLTAGE_CONV:inst4|TEMP[1] } "NODE_NAME" } } }  } 0}
{ "Info" "ITDB_TSU_RESULT" "AD_SRAM:inst2\|WR ADIN\[2\] CLK 11.709 ns register " "Info: tsu for register AD_SRAM:inst2\|WR (data pin = ADIN\[2\], clock pin = CLK) is 11.709 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "14.393 ns + Longest pin register " "Info: + Longest pin to register delay is 14.393 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.475 ns) 1.475 ns ADIN\[2\] 1 PIN PIN_52 2 " "Info: 1: + IC(0.000 ns) + CELL(1.475 ns) = 1.475 ns; Loc. = PIN_52; Fanout = 2; PIN Node = 'ADIN\[2\]'" {  } { { "e:/ywh/quartusii/scanwave/db/TEST_cmp.qrpt" "" "" { Report "e:/ywh/quartusii/scanwave/db/TEST_cmp.qrpt" Compiler "TEST" "UNKNOWN" "V1" "e:/ywh/quartusii/scanwave/db/TEST.quartus_db" { Floorplan "" "" "" { ADIN[2] } "NODE_NAME" } } } { "e:/ywh/quartusii/scanwave/test.bdf" "" "" { Schematic "e:/ywh/quartusii/scanwave/test.bdf" { { 328 72 240 344 "ADIN\[7..0\]" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(6.461 ns) + CELL(0.590 ns) 8.526 ns MAX114:39\|\\PRO:Q\[2\]~46 2 COMB LC_X21_Y5_N2 3 " "Info: 2: + IC(6.461 ns) + CELL(0.590 ns) = 8.526 ns; Loc. = LC_X21_Y5_N2; Fanout = 3; COMB Node = 'MAX114:39\|\\PRO:Q\[2\]~46'" {  } { { "e:/ywh/quartusii/scanwave/db/TEST_cmp.qrpt" "" "" { Report "e:/ywh/quartusii/scanwave/db/TEST_cmp.qrpt" Compiler "TEST" "UNKNOWN" "V1" "e:/ywh/quartusii/scanwave/db/TEST.quartus_db" { Floorplan "" "" "7.051 ns" { ADIN[2] MAX114:39|\PRO:Q[2]~46 } "NODE_NAME" } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.538 ns) + CELL(0.564 ns) 10.628 ns CONV_SINGLE:inst5\|LessThan~3COUT0 3 COMB LC_X23_Y4_N2 1 " "Info: 3: + IC(1.538 ns) + CELL(0.564 ns) = 10.628 ns; Loc. = LC_X23_Y4_N2; Fanout = 1; COMB Node = 'CONV_SINGLE:inst5\|LessThan~3COUT0'" {  } { { "e:/ywh/quartusii/scanwave/db/TEST_cmp.qrpt" "" "" { Report "e:/ywh/quartusii/scanwave/db/TEST_cmp.qrpt" Compiler "TEST" "UNKNOWN" "V1" "e:/ywh/quartusii/scanwave/db/TEST.quartus_db" { Floorplan "" "" "2.102 ns" { MAX114:39|\PRO:Q[2]~46 CONV_SINGLE:inst5|LessThan~3COUT0 } "NODE_NAME" } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.078 ns) 10.706 ns CONV_SINGLE:inst5\|LessThan~4COUT0 4 COMB LC_X23_Y4_N3 1 " "Info: 4: + IC(0.000 ns) + CELL(0.078 ns) = 10.706 ns; Loc. = LC_X23_Y4_N3; Fanout = 1; COMB Node = 'CONV_SINGLE:inst5\|LessThan~4COUT0'" {  } { { "e:/ywh/quartusii/scanwave/db/TEST_cmp.qrpt" "" "" { Report "e:/ywh/quartusii/scanwave/db/TEST_cmp.qrpt" Compiler "TEST" "UNKNOWN" "V1" "e:/ywh/quartusii/scanwave/db/TEST.quartus_db" { Floorplan "" "" "0.078 ns" { CONV_SINGLE:inst5|LessThan~3COUT0 CONV_SINGLE:inst5|LessThan~4COUT0 } "NODE_NAME" } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.178 ns) 10.884 ns CONV_SINGLE:inst5\|LessThan~5 5 COMB LC_X23_Y4_N4 1 " "Info: 5: + IC(0.000 ns) + CELL(0.178 ns) = 10.884 ns; Loc. = LC_X23_Y4_N4; Fanout = 1; COMB Node = 'CONV_SINGLE:inst5\|LessThan~5'" {  } { { "e:/ywh/quartusii/scanwave/db/TEST_cmp.qrpt" "" "" { Report "e:/ywh/quartusii/scanwave/db/TEST_cmp.qrpt" Compiler "TEST" "UNKNOWN" "V1" "e:/ywh/quartusii/scanwave/db/TEST.quartus_db" { Floorplan "" "" "0.178 ns" { CONV_SINGLE:inst5|LessThan~4COUT0 CONV_SINGLE:inst5|LessThan~5 } "NODE_NAME" } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.621 ns) 11.505 ns CONV_SINGLE:inst5\|LessThan~8 6 COMB LC_X23_Y4_N7 1 " "Info: 6: + IC(0.000 ns) + CELL(0.621 ns) = 11.505 ns; Loc. = LC_X23_Y4_N7; Fanout = 1; COMB Node = 'CONV_SINGLE:inst5\|LessThan~8'" {  } { { "e:/ywh/quartusii/scanwave/db/TEST_cmp.qrpt" "" "" { Report "e:/ywh/quartusii/scanwave/db/TEST_cmp.qrpt" Compiler "TEST" "UNKNOWN" "V1" "e:/ywh/quartusii/scanwave/db/TEST.quartus_db" { Floorplan "" "" "0.621 ns" { CONV_SINGLE:inst5|LessThan~5 CONV_SINGLE:inst5|LessThan~8 } "NODE_NAME" } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.182 ns) + CELL(0.114 ns) 11.801 ns CONV_SINGLE:inst5\|process0~0 7 COMB LC_X23_Y4_N8 16 " "Info: 7: + IC(0.182 ns) + CELL(0.114 ns) = 11.801 ns; Loc. = LC_X23_Y4_N8; Fanout = 16; COMB Node = 'CONV_SINGLE:inst5\|process0~0'" {  } { { "e:/ywh/quartusii/scanwave/db/TEST_cmp.qrpt" "" "" { Report "e:/ywh/quartusii/scanwave/db/TEST_cmp.qrpt" Compiler "TEST" "UNKNOWN" "V1" "e:/ywh/quartusii/scanwave/db/TEST.quartus_db" { Floorplan "" "" "0.296 ns" { CONV_SINGLE:inst5|LessThan~8 CONV_SINGLE:inst5|process0~0 } "NODE_NAME" } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.152 ns) + CELL(0.114 ns) 13.067 ns AD_SRAM:inst2\|WR~0 8 COMB LC_X21_Y4_N2 1 " "Info: 8: + IC(1.152 ns) + CELL(0.114 ns) = 13.067 ns; Loc. = LC_X21_Y4_N2; Fanout = 1; COMB Node = 'AD_SRAM:inst2\|WR~0'" {  } { { "e:/ywh/quartusii/scanwave/db/TEST_cmp.qrpt" "" "" { Report "e:/ywh/quartusii/scanwave/db/TEST_cmp.qrpt" Compiler "TEST" "UNKNOWN" "V1" "e:/ywh/quartusii/scanwave/db/TEST.quartus_db" { Floorplan "" "" "1.266 ns" { CONV_SINGLE:inst5|process0~0 AD_SRAM:inst2|WR~0 } "NODE_NAME" } } } { "E:/ywh/QUARTUSII/scanwave/AD_SRAM.vhd" "" "" { Text "E:/ywh/QUARTUSII/scanwave/AD_SRAM.vhd" 24 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.459 ns) + CELL(0.867 ns) 14.393 ns AD_SRAM:inst2\|WR 9 REG LC_X21_Y4_N7 12 " "Info: 9: + IC(0.459 ns) + CELL(0.867 ns) = 14.393 ns; Loc. = LC_X21_Y4_N7; Fanout = 12; REG Node = 'AD_SRAM:inst2\|WR'" {  } { { "e:/ywh/quartusii/scanwave/db/TEST_cmp.qrpt" "" "" { Report "e:/ywh/quartusii/scanwave/db/TEST_cmp.qrpt" Compiler "TEST" "UNKNOWN" "V1" "e:/ywh/quartusii/scanwave/db/TEST.quartus_db" { Floorplan "" "" "1.326 ns" { AD_SRAM:inst2|WR~0 AD_SRAM:inst2|WR } "NODE_NAME" } } } { "E:/ywh/QUARTUSII/scanwave/AD_SRAM.vhd" "" "" { Text "E:/ywh/QUARTUSII/scanwave/AD_SRAM.vhd" 24 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.601 ns 31.97 % " "Info: Total cell delay = 4.601 ns ( 31.97 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "9.792 ns 68.03 % " "Info: Total interconnect delay = 9.792 ns ( 68.03 % )" {  } {  } 0}  } { { "e:/ywh/quartusii/scanwave/db/TEST_cmp.qrpt" "" "" { Report "e:/ywh/quartusii/scanwave/db/TEST_cmp.qrpt" Compiler "TEST" "UNKNOWN" "V1" "e:/ywh/quartusii/scanwave/db/TEST.quartus_db" { Floorplan "" "" "14.393 ns" { ADIN[2] MAX114:39|\PRO:Q[2]~46 CONV_SINGLE:inst5|LessThan~3COUT0 CONV_SINGLE:inst5|LessThan~4COUT0 CONV_SINGLE:inst5|LessThan~5 CONV_SINGLE:inst5|LessThan~8 CONV_SINGLE:inst5|process0~0 AD_SRAM:inst2|WR~0 AD_SRAM:inst2|WR } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" {  } { { "E:/ywh/QUARTUSII/scanwave/AD_SRAM.vhd" "" "" { Text "E:/ywh/QUARTUSII/scanwave/AD_SRAM.vhd" 24 -1 0 } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK destination 2.721 ns - Shortest register " "Info: - Shortest clock path from clock CLK to destination register is 2.721 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns CLK 1 CLK PIN_17 213 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_17; Fanout = 213; CLK Node = 'CLK'" {  } { { "e:/ywh/quartusii/scanwave/db/TEST_cmp.qrpt" "" "" { Report "e:/ywh/quartusii/scanwave/db/TEST_cmp.qrpt" Compiler "TEST" "UNKNOWN" "V1" "e:/ywh/quartusii/scanwave/db/TEST.quartus_db" { Floorplan "" "" "" { CLK } "NODE_NAME" } } } { "e:/ywh/quartusii/scanwave/test.bdf" "" "" { Schematic "e:/ywh/quartusii/scanwave/test.bdf" { { 512 32 200 528 "CLK" "" } { 336 280 312 352 "CLK" "" } { 352 960 984 368 "CLK" "" } { 368 960 984 384 "CLK" "" } { 504 200 264 520 "CLK" "" } { 272 616 656 288 "CLK" "" } { 816 200 240 832 "CLK" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.541 ns) + CELL(0.711 ns) 2.721 ns AD_SRAM:inst2\|WR 2 REG LC_X21_Y4_N7 12 " "Info: 2: + IC(0.541 ns) + CELL(0.711 ns) = 2.721 ns; Loc. = LC_X21_Y4_N7; Fanout = 12; REG Node = 'AD_SRAM:inst2\|WR'" {  } { { "e:/ywh/quartusii/scanwave/db/TEST_cmp.qrpt" "" "" { Report "e:/ywh/quartusii/scanwave/db/TEST_cmp.qrpt" Compiler "TEST" "UNKNOWN" "V1" "e:/ywh/quartusii/scanwave/db/TEST.quartus_db" { Floorplan "" "" "1.252 ns" { CLK AD_SRAM:inst2|WR } "NODE_NAME" } } } { "E:/ywh/QUARTUSII/scanwave/AD_SRAM.vhd" "" "" { Text "E:/ywh/QUARTUSII/scanwave/AD_SRAM.vhd" 24 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns 80.12 % " "Info: Total cell delay = 2.180 ns ( 80.12 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.541 ns 19.88 % " "Info: Total interconnect delay = 0.541 ns ( 19.88 % )" {  } {  } 0}  } { { "e:/ywh/quartusii/scanwave/db/TEST_cmp.qrpt" "" "" { Report "e:/ywh/quartusii/scanwave/db/TEST_cmp.qrpt" Compiler "TEST" "UNKNOWN" "V1" "e:/ywh/quartusii/scanwave/db/TEST.quartus_db" { Floorplan "" "" "2.721 ns" { CLK AD_SRAM:inst2|WR } "NODE_NAME" } } }  } 0}  } { { "e:/ywh/quartusii/scanwave/db/TEST_cmp.qrpt" "" "" { Report "e:/ywh/quartusii/scanwave/db/TEST_cmp.qrpt" Compiler "TEST" "UNKNOWN" "V1" "e:/ywh/quartusii/scanwave/db/TEST.quartus_db" { Floorplan "" "" "14.393 ns" { ADIN[2] MAX114:39|\PRO:Q[2]~46 CONV_SINGLE:inst5|LessThan~3COUT0 CONV_SINGLE:inst5|LessThan~4COUT0 CONV_SINGLE:inst5|LessThan~5 CONV_SINGLE:inst5|LessThan~8 CONV_SINGLE:inst5|process0~0 AD_SRAM:inst2|WR~0 AD_SRAM:inst2|WR } "NODE_NAME" } } } { "e:/ywh/quartusii/scanwave/db/TEST_cmp.qrpt" "" "" { Report "e:/ywh/quartusii/scanwave/db/TEST_cmp.qrpt" Compiler "TEST" "UNKNOWN" "V1" "e:/ywh/quartusii/scanwave/db/TEST.quartus_db" { Floorplan "" "" "2.721 ns" { CLK AD_SRAM:inst2|WR } "NODE_NAME" } } }  } 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "CLK DAOUT\[5\] VOLTAGE_CONV:inst4\|TEMP\[5\] 13.348 ns register " "Info: tco from clock CLK to destination pin DAOUT\[5\] through register VOLTAGE_CONV:inst4\|TEMP\[5\] is 13.348 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK source 8.410 ns + Longest register " "Info: + Longest clock path from clock CLK to source register is 8.410 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns CLK 1 CLK PIN_17 213 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_17; Fanout = 213; CLK Node = 'CLK'" {  } { { "e:/ywh/quartusii/scanwave/db/TEST_cmp.qrpt" "" "" { Report "e:/ywh/quartusii/scanwave/db/TEST_cmp.qrpt" Compiler "TEST" "UNKNOWN" "V1" "e:/ywh/quartusii/scanwave/db/TEST.quartus_db" { Floorplan "" "" "" { CLK } "NODE_NAME" } } } { "e:/ywh/quartusii/scanwave/test.bdf" "" "" { Schematic "e:/ywh/quartusii/scanwave/test.bdf" { { 512 32 200 528 "CLK" "" } { 336 280 312 352 "CLK" "" } { 352 960 984 368 "CLK" "" } { 368 960 984 384 "CLK" "" } { 504 200 264 520 "CLK" "" } { 272 616 656 288 "CLK" "" } { 816 200 240 832 "CLK" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.541 ns) + CELL(0.935 ns) 2.945 ns AD_SRAM:inst2\|WR 2 REG LC_X21_Y4_N7 12 " "Info: 2: + IC(0.541 ns) + CELL(0.935 ns) = 2.945 ns; Loc. = LC_X21_Y4_N7; Fanout = 12; REG Node = 'AD_SRAM:inst2\|WR'" {  } { { "e:/ywh/quartusii/scanwave/db/TEST_cmp.qrpt" "" "" { Report "e:/ywh/quartusii/scanwave/db/TEST_cmp.qrpt" Compiler "TEST" "UNKNOWN" "V1" "e:/ywh/quartusii/scanwave/db/TEST.quartus_db" { Floorplan "" "" "1.476 ns" { CLK AD_SRAM:inst2|WR } "NODE_NAME" } } } { "E:/ywh/QUARTUSII/scanwave/AD_SRAM.vhd" "" "" { Text "E:/ywh/QUARTUSII/scanwave/AD_SRAM.vhd" 24 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(4.754 ns) + CELL(0.711 ns) 8.410 ns VOLTAGE_CONV:inst4\|TEMP\[5\] 3 REG LC_X16_Y6_N5 1 " "Info: 3: + IC(4.754 ns) + CELL(0.711 ns) = 8.410 ns; Loc. = LC_X16_Y6_N5; Fanout = 1; REG Node = 'VOLTAGE_CONV:inst4\|TEMP\[5\]'" {  } { { "e:/ywh/quartusii/scanwave/db/TEST_cmp.qrpt" "" "" { Report "e:/ywh/quartusii/scanwave/db/TEST_cmp.qrpt" Compiler "TEST" "UNKNOWN" "V1" "e:/ywh/quartusii/scanwave/db/TEST.quartus_db" { Floorplan "" "" "5.465 ns" { AD_SRAM:inst2|WR VOLTAGE_CONV:inst4|TEMP[5] } "NODE_NAME" } } } { "E:/ywh/QUARTUSII/scanwave/VOLTAGE_CONV.vhd" "" "" { Text "E:/ywh/QUARTUSII/scanwave/VOLTAGE_CONV.vhd" 35 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.115 ns 37.04 % " "Info: Total cell delay = 3.115 ns ( 37.04 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.295 ns 62.96 % " "Info: Total interconnect delay = 5.295 ns ( 62.96 % )" {  } {  } 0}  } { { "e:/ywh/quartusii/scanwave/db/TEST_cmp.qrpt" "" "" { Report "e:/ywh/quartusii/scanwave/db/TEST_cmp.qrpt" Compiler "TEST" "UNKNOWN" "V1" "e:/ywh/quartusii/scanwave/db/TEST.quartus_db" { Floorplan "" "" "8.410 ns" { CLK AD_SRAM:inst2|WR VOLTAGE_CONV:inst4|TEMP[5] } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "E:/ywh/QUARTUSII/scanwave/VOLTAGE_CONV.vhd" "" "" { Text "E:/ywh/QUARTUSII/scanwave/VOLTAGE_CONV.vhd" 35 -1 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.714 ns + Longest register pin " "Info: + Longest register to pin delay is 4.714 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns VOLTAGE_CONV:inst4\|TEMP\[5\] 1 REG LC_X16_Y6_N5 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X16_Y6_N5; Fanout = 1; REG Node = 'VOLTAGE_CONV:inst4\|TEMP\[5\]'" {  } { { "e:/ywh/quartusii/scanwave/db/TEST_cmp.qrpt" "" "" { Report "e:/ywh/quartusii/scanwave/db/TEST_cmp.qrpt" Compiler "TEST" "UNKNOWN" "V1" "e:/ywh/quartusii/scanwave/db/TEST.quartus_db" { Floorplan "" "" "" { VOLTAGE_CONV:inst4|TEMP[5] } "NODE_NAME" } } } { "E:/ywh/QUARTUSII/scanwave/VOLTAGE_CONV.vhd" "" "" { Text "E:/ywh/QUARTUSII/scanwave/VOLTAGE_CONV.vhd" 35 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.606 ns) + CELL(2.108 ns) 4.714 ns DAOUT\[5\] 2 PIN PIN_49 0 " "Info: 2: + IC(2.606 ns) + CELL(2.108 ns) = 4.714 ns; Loc. = PIN_49; Fanout = 0; PIN Node = 'DAOUT\[5\]'" {  } { { "e:/ywh/quartusii/scanwave/db/TEST_cmp.qrpt" "" "" { Report "e:/ywh/quartusii/scanwave/db/TEST_cmp.qrpt" Compiler "TEST" "UNKNOWN" "V1" "e:/ywh/quartusii/scanwave/db/TEST.quartus_db" { Floorplan "" "" "4.714 ns" { VOLTAGE_CONV:inst4|TEMP[5] DAOUT[5] } "NODE_NAME" } } } { "e:/ywh/quartusii/scanwave/test.bdf" "" "" { Schematic "e:/ywh/quartusii/scanwave/test.bdf" { { 320 1480 1656 336 "DAOUT\[7..0\]" "" } } } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.108 ns 44.72 % " "Info: Total cell delay = 2.108 ns ( 44.72 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.606 ns 55.28 % " "Info: Total interconnect delay = 2.606 ns ( 55.28 % )" {  } {  } 0}  } { { "e:/ywh/quartusii/scanwave/db/TEST_cmp.qrpt" "" "" { Report "e:/ywh/quartusii/scanwave/db/TEST_cmp.qrpt" Compiler "TEST" "UNKNOWN" "V1" "e:/ywh/quartusii/scanwave/db/TEST.quartus_db" { Floorplan "" "" "4.714 ns" { VOLTAGE_CONV:inst4|TEMP[5] DAOUT[5] } "NODE_NAME" } } }  } 0}  } { { "e:/ywh/quartusii/scanwave/db/TEST_cmp.qrpt" "" "" { Report "e:/ywh/quartusii/scanwave/db/TEST_cmp.qrpt" Compiler "TEST" "UNKNOWN" "V1" "e:/ywh/quartusii/scanwave/db/TEST.quartus_db" { Floorplan "" "" "8.410 ns" { CLK AD_SRAM:inst2|WR VOLTAGE_CONV:inst4|TEMP[5] } "NODE_NAME" } } } { "e:/ywh/quartusii/scanwave/db/TEST_cmp.qrpt" "" "" { Report "e:/ywh/quartusii/scanwave/db/TEST_cmp.qrpt" Compiler "TEST" "UNKNOWN" "V1" "e:/ywh/quartusii/scanwave/db/TEST.quartus_db" { Floorplan "" "" "4.714 ns" { VOLTAGE_CONV:inst4|TEMP[5] DAOUT[5] } "NODE_NAME" } } }  } 0}