test.tan.qmsg

数字示波器的FPGA实现 VHDL编写 Quartus7.1测试通过

{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "CLK " "Info: Assuming node CLK is an undefined clock" {  } { { "e:/ywh/quartusii/scanwave/test.bdf" "" "" { Schematic "e:/ywh/quartusii/scanwave/test.bdf" { { 512 32 200 528 "CLK" "" } { 336 280 312 352 "CLK" "" } { 352 960 984 368 "CLK" "" } { 368 960 984 384 "CLK" "" } { 504 200 264 520 "CLK" "" } { 272 616 656 288 "CLK" "" } { 816 200 240 832 "CLK" "" } } } } { "c:/altera/quartus41/bin/Assignment Editor.qase" "" "" { Assignment "c:/altera/quartus41/bin/Assignment Editor.qase" 1 { { 0 "CLK" } } } }  } 0} { "Info" "ITAN_NODE_MAP_TO_CLK" "ALE " "Info: Assuming node ALE is an undefined clock" {  } { { "e:/ywh/quartusii/scanwave/test.bdf" "" "" { Schematic "e:/ywh/quartusii/scanwave/test.bdf" { { 776 32 200 792 "ALE" "" } } } } { "c:/altera/quartus41/bin/Assignment Editor.qase" "" "" { Assignment "c:/altera/quartus41/bin/Assignment Editor.qase" 1 { { 0 "ALE" } } } }  } 0}  } {  } 0}
{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "5 " "Warning: Found 5 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_RIPPLE_CLK" "FREDEVIDER8:78\|CLK " "Info: Detected ripple clock FREDEVIDER8:78\|CLK as buffer" {  } { { "E:/ywh/QUARTUSII/scanwave/FREDEVIDER8.vhd" "" "" { Text "E:/ywh/QUARTUSII/scanwave/FREDEVIDER8.vhd" 17 -1 0 } } { "c:/altera/quartus41/bin/Assignment Editor.qase" "" "" { Assignment "c:/altera/quartus41/bin/Assignment Editor.qase" 1 { { 0 "FREDEVIDER8:78\|CLK" } } } }  } 0} { "Info" "ITAN_RIPPLE_CLK" "MAX114:39\|CURRENT_STATE~11 " "Info: Detected ripple clock MAX114:39\|CURRENT_STATE~11 as buffer" {  } { { "c:/altera/quartus41/bin/Assignment Editor.qase" "" "" { Assignment "c:/altera/quartus41/bin/Assignment Editor.qase" 1 { { 0 "MAX114:39\|CURRENT_STATE~11" } } } }  } 0} { "Info" "ITAN_GATED_CLK" "MAX114:39\|SAVE~29 " "Info: Detected gated clock MAX114:39\|SAVE~29 as buffer" {  } { { "e:/ywh/quartusii/scanwave/MAX114.vhd" "" "" { Text "e:/ywh/quartusii/scanwave/MAX114.vhd" 6 -1 0 } } { "c:/altera/quartus41/bin/Assignment Editor.qase" "" "" { Assignment "c:/altera/quartus41/bin/Assignment Editor.qase" 1 { { 0 "MAX114:39\|SAVE~29" } } } }  } 0} { "Info" "ITAN_RIPPLE_CLK" "AD_SRAM:inst2\|WR " "Info: Detected ripple clock AD_SRAM:inst2\|WR as buffer" {  } { { "E:/ywh/QUARTUSII/scanwave/AD_SRAM.vhd" "" "" { Text "E:/ywh/QUARTUSII/scanwave/AD_SRAM.vhd" 24 -1 0 } } { "c:/altera/quartus41/bin/Assignment Editor.qase" "" "" { Assignment "c:/altera/quartus41/bin/Assignment Editor.qase" 1 { { 0 "AD_SRAM:inst2\|WR" } } } }  } 0} { "Info" "ITAN_RIPPLE_CLK" "MAX114:39\|CURRENT_STATE~15 " "Info: Detected ripple clock MAX114:39\|CURRENT_STATE~15 as buffer" {  } { { "c:/altera/quartus41/bin/Assignment Editor.qase" "" "" { Assignment "c:/altera/quartus41/bin/Assignment Editor.qase" 1 { { 0 "MAX114:39\|CURRENT_STATE~15" } } } }  } 0}  } {  } 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "CLK register BUS_1:inst9\|RAMTMP7\[0\] register AD_SRAM:inst2\|WR 93.32 MHz 10.716 ns Internal " "Info: Clock CLK has Internal fmax of 93.32 MHz between source register BUS_1:inst9\|RAMTMP7\[0\] and destination register AD_SRAM:inst2\|WR (period= 10.716 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.097 ns + Longest register register " "Info: + Longest register to register delay is 5.097 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns BUS_1:inst9\|RAMTMP7\[0\] 1 REG LC_X24_Y4_N9 3 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X24_Y4_N9; Fanout = 3; REG Node = 'BUS_1:inst9\|RAMTMP7\[0\]'" {  } { { "e:/ywh/quartusii/scanwave/db/TEST_cmp.qrpt" "" "" { Report "e:/ywh/quartusii/scanwave/db/TEST_cmp.qrpt" Compiler "TEST" "UNKNOWN" "V1" "e:/ywh/quartusii/scanwave/db/TEST.quartus_db" { Floorplan "" "" "" { BUS_1:inst9|RAMTMP7[0] } "NODE_NAME" } } } { "e:/ywh/quartusii/scanwave/BUS_1.vhd" "" "" { Text "e:/ywh/quartusii/scanwave/BUS_1.vhd" 56 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.753 ns) + CELL(0.423 ns) 1.176 ns CONV_SINGLE:inst5\|LessThan~1COUT0 2 COMB LC_X23_Y4_N0 1 " "Info: 2: + IC(0.753 ns) + CELL(0.423 ns) = 1.176 ns; Loc. = LC_X23_Y4_N0; Fanout = 1; COMB Node = 'CONV_SINGLE:inst5\|LessThan~1COUT0'" {  } { { "e:/ywh/quartusii/scanwave/db/TEST_cmp.qrpt" "" "" { Report "e:/ywh/quartusii/scanwave/db/TEST_cmp.qrpt" Compiler "TEST" "UNKNOWN" "V1" "e:/ywh/quartusii/scanwave/db/TEST.quartus_db" { Floorplan "" "" "1.176 ns" { BUS_1:inst9|RAMTMP7[0] CONV_SINGLE:inst5|LessThan~1COUT0 } "NODE_NAME" } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.078 ns) 1.254 ns CONV_SINGLE:inst5\|LessThan~2COUT0 3 COMB LC_X23_Y4_N1 1 " "Info: 3: + IC(0.000 ns) + CELL(0.078 ns) = 1.254 ns; Loc. = LC_X23_Y4_N1; Fanout = 1; COMB Node = 'CONV_SINGLE:inst5\|LessThan~2COUT0'" {  } { { "e:/ywh/quartusii/scanwave/db/TEST_cmp.qrpt" "" "" { Report "e:/ywh/quartusii/scanwave/db/TEST_cmp.qrpt" Compiler "TEST" "UNKNOWN" "V1" "e:/ywh/quartusii/scanwave/db/TEST.quartus_db" { Floorplan "" "" "0.078 ns" { CONV_SINGLE:inst5|LessThan~1COUT0 CONV_SINGLE:inst5|LessThan~2COUT0 } "NODE_NAME" } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.078 ns) 1.332 ns CONV_SINGLE:inst5\|LessThan~3COUT0 4 COMB LC_X23_Y4_N2 1 " "Info: 4: + IC(0.000 ns) + CELL(0.078 ns) = 1.332 ns; Loc. = LC_X23_Y4_N2; Fanout = 1; COMB Node = 'CONV_SINGLE:inst5\|LessThan~3COUT0'" {  } { { "e:/ywh/quartusii/scanwave/db/TEST_cmp.qrpt" "" "" { Report "e:/ywh/quartusii/scanwave/db/TEST_cmp.qrpt" Compiler "TEST" "UNKNOWN" "V1" "e:/ywh/quartusii/scanwave/db/TEST.quartus_db" { Floorplan "" "" "0.078 ns" { CONV_SINGLE:inst5|LessThan~2COUT0 CONV_SINGLE:inst5|LessThan~3COUT0 } "NODE_NAME" } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.078 ns) 1.410 ns CONV_SINGLE:inst5\|LessThan~4COUT0 5 COMB LC_X23_Y4_N3 1 " "Info: 5: + IC(0.000 ns) + CELL(0.078 ns) = 1.410 ns; Loc. = LC_X23_Y4_N3; Fanout = 1; COMB Node = 'CONV_SINGLE:inst5\|LessThan~4COUT0'" {  } { { "e:/ywh/quartusii/scanwave/db/TEST_cmp.qrpt" "" "" { Report "e:/ywh/quartusii/scanwave/db/TEST_cmp.qrpt" Compiler "TEST" "UNKNOWN" "V1" "e:/ywh/quartusii/scanwave/db/TEST.quartus_db" { Floorplan "" "" "0.078 ns" { CONV_SINGLE:inst5|LessThan~3COUT0 CONV_SINGLE:inst5|LessThan~4COUT0 } "NODE_NAME" } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.178 ns) 1.588 ns CONV_SINGLE:inst5\|LessThan~5 6 COMB LC_X23_Y4_N4 1 " "Info: 6: + IC(0.000 ns) + CELL(0.178 ns) = 1.588 ns; Loc. = LC_X23_Y4_N4; Fanout = 1; COMB Node = 'CONV_SINGLE:inst5\|LessThan~5'" {  } { { "e:/ywh/quartusii/scanwave/db/TEST_cmp.qrpt" "" "" { Report "e:/ywh/quartusii/scanwave/db/TEST_cmp.qrpt" Compiler "TEST" "UNKNOWN" "V1" "e:/ywh/quartusii/scanwave/db/TEST.quartus_db" { Floorplan "" "" "0.178 ns" { CONV_SINGLE:inst5|LessThan~4COUT0 CONV_SINGLE:inst5|LessThan~5 } "NODE_NAME" } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.621 ns) 2.209 ns CONV_SINGLE:inst5\|LessThan~8 7 COMB LC_X23_Y4_N7 1 " "Info: 7: + IC(0.000 ns) + CELL(0.621 ns) = 2.209 ns; Loc. = LC_X23_Y4_N7; Fanout = 1; COMB Node = 'CONV_SINGLE:inst5\|LessThan~8'" {  } { { "e:/ywh/quartusii/scanwave/db/TEST_cmp.qrpt" "" "" { Report "e:/ywh/quartusii/scanwave/db/TEST_cmp.qrpt" Compiler "TEST" "UNKNOWN" "V1" "e:/ywh/quartusii/scanwave/db/TEST.quartus_db" { Floorplan "" "" "0.621 ns" { CONV_SINGLE:inst5|LessThan~5 CONV_SINGLE:inst5|LessThan~8 } "NODE_NAME" } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.182 ns) + CELL(0.114 ns) 2.505 ns CONV_SINGLE:inst5\|process0~0 8 COMB LC_X23_Y4_N8 16 " "Info: 8: + IC(0.182 ns) + CELL(0.114 ns) = 2.505 ns; Loc. = LC_X23_Y4_N8; Fanout = 16; COMB Node = 'CONV_SINGLE:inst5\|process0~0'" {  } { { "e:/ywh/quartusii/scanwave/db/TEST_cmp.qrpt" "" "" { Report "e:/ywh/quartusii/scanwave/db/TEST_cmp.qrpt" Compiler "TEST" "UNKNOWN" "V1" "e:/ywh/quartusii/scanwave/db/TEST.quartus_db" { Floorplan "" "" "0.296 ns" { CONV_SINGLE:inst5|LessThan~8 CONV_SINGLE:inst5|process0~0 } "NODE_NAME" } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.152 ns) + CELL(0.114 ns) 3.771 ns AD_SRAM:inst2\|WR~0 9 COMB LC_X21_Y4_N2 1 " "Info: 9: + IC(1.152 ns) + CELL(0.114 ns) = 3.771 ns; Loc. = LC_X21_Y4_N2; Fanout = 1; COMB Node = 'AD_SRAM:inst2\|WR~0'" {  } { { "e:/ywh/quartusii/scanwave/db/TEST_cmp.qrpt" "" "" { Report "e:/ywh/quartusii/scanwave/db/TEST_cmp.qrpt" Compiler "TEST" "UNKNOWN" "V1" "e:/ywh/quartusii/scanwave/db/TEST.quartus_db" { Floorplan "" "" "1.266 ns" { CONV_SINGLE:inst5|process0~0 AD_SRAM:inst2|WR~0 } "NODE_NAME" } } } { "E:/ywh/QUARTUSII/scanwave/AD_SRAM.vhd" "" "" { Text "E:/ywh/QUARTUSII/scanwave/AD_SRAM.vhd" 24 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.459 ns) + CELL(0.867 ns) 5.097 ns AD_SRAM:inst2\|WR 10 REG LC_X21_Y4_N7 12 " "Info: 10: + IC(0.459 ns) + CELL(0.867 ns) = 5.097 ns; Loc. = LC_X21_Y4_N7; Fanout = 12; REG Node = 'AD_SRAM:inst2\|WR'" {  } { { "e:/ywh/quartusii/scanwave/db/TEST_cmp.qrpt" "" "" { Report "e:/ywh/quartusii/scanwave/db/TEST_cmp.qrpt" Compiler "TEST" "UNKNOWN" "V1" "e:/ywh/quartusii/scanwave/db/TEST.quartus_db" { Floorplan "" "" "1.326 ns" { AD_SRAM:inst2|WR~0 AD_SRAM:inst2|WR } "NODE_NAME" } } } { "E:/ywh/QUARTUSII/scanwave/AD_SRAM.vhd" "" "" { Text "E:/ywh/QUARTUSII/scanwave/AD_SRAM.vhd" 24 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.551 ns 50.05 % " "Info: Total cell delay = 2.551 ns ( 50.05 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.546 ns 49.95 % " "Info: Total interconnect delay = 2.546 ns ( 49.95 % )" {  } {  } 0}  } { { "e:/ywh/quartusii/scanwave/db/TEST_cmp.qrpt" "" "" { Report "e:/ywh/quartusii/scanwave/db/TEST_cmp.qrpt" Compiler "TEST" "UNKNOWN" "V1" "e:/ywh/quartusii/scanwave/db/TEST.quartus_db" { Floorplan "" "" "5.097 ns" { BUS_1:inst9|RAMTMP7[0] CONV_SINGLE:inst5|LessThan~1COUT0 CONV_SINGLE:inst5|LessThan~2COUT0 CONV_SINGLE:inst5|LessThan~3COUT0 CONV_SINGLE:inst5|LessThan~4COUT0 CONV_SINGLE:inst5|LessThan~5 CONV_SINGLE:inst5|LessThan~8 CONV_SINGLE:inst5|process0~0 AD_SRAM:inst2|WR~0 AD_SRAM:inst2|WR } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK destination 2.721 ns + Shortest register " "Info: + Shortest clock path from clock CLK to destination register is 2.721 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns CLK 1 CLK PIN_17 213 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_17; Fanout = 213; CLK Node = 'CLK'" {  } { { "e:/ywh/quartusii/scanwave/db/TEST_cmp.qrpt" "" "" { Report "e:/ywh/quartusii/scanwave/db/TEST_cmp.qrpt" Compiler "TEST" "UNKNOWN" "V1" "e:/ywh/quartusii/scanwave/db/TEST.quartus_db" { Floorplan "" "" "" { CLK } "NODE_NAME" } } } { "e:/ywh/quartusii/scanwave/test.bdf" "" "" { Schematic "e:/ywh/quartusii/scanwave/test.bdf" { { 512 32 200 528 "CLK" "" } { 336 280 312 352 "CLK" "" } { 352 960 984 368 "CLK" "" } { 368 960 984 384 "CLK" "" } { 504 200 264 520 "CLK" "" } { 272 616 656 288 "CLK" "" } { 816 200 240 832 "CLK" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.541 ns) + CELL(0.711 ns) 2.721 ns AD_SRAM:inst2\|WR 2 REG LC_X21_Y4_N7 12 " "Info: 2: + IC(0.541 ns) + CELL(0.711 ns) = 2.721 ns; Loc. = LC_X21_Y4_N7; Fanout = 12; REG Node = 'AD_SRAM:inst2\|WR'" {  } { { "e:/ywh/quartusii/scanwave/db/TEST_cmp.qrpt" "" "" { Report "e:/ywh/quartusii/scanwave/db/TEST_cmp.qrpt" Compiler "TEST" "UNKNOWN" "V1" "e:/ywh/quartusii/scanwave/db/TEST.quartus_db" { Floorplan "" "" "1.252 ns" { CLK AD_SRAM:inst2|WR } "NODE_NAME" } } } { "E:/ywh/QUARTUSII/scanwave/AD_SRAM.vhd" "" "" { Text "E:/ywh/QUARTUSII/scanwave/AD_SRAM.vhd" 24 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns 80.12 % " "Info: Total cell delay = 2.180 ns ( 80.12 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.541 ns 19.88 % " "Info: Total interconnect delay = 0.541 ns ( 19.88 % )" {  } {  } 0}  } { { "e:/ywh/quartusii/scanwave/db/TEST_cmp.qrpt" "" "" { Report "e:/ywh/quartusii/scanwave/db/TEST_cmp.qrpt" Compiler "TEST" "UNKNOWN" "V1" "e:/ywh/quartusii/scanwave/db/TEST.quartus_db" { Floorplan "" "" "2.721 ns" { CLK AD_SRAM:inst2|WR } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK source 2.721 ns - Longest register " "Info: - Longest clock path from clock CLK to source register is 2.721 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns CLK 1 CLK PIN_17 213 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_17; Fanout = 213; CLK Node = 'CLK'" {  } { { "e:/ywh/quartusii/scanwave/db/TEST_cmp.qrpt" "" "" { Report "e:/ywh/quartusii/scanwave/db/TEST_cmp.qrpt" Compiler "TEST" "UNKNOWN" "V1" "e:/ywh/quartusii/scanwave/db/TEST.quartus_db" { Floorplan "" "" "" { CLK } "NODE_NAME" } } } { "e:/ywh/quartusii/scanwave/test.bdf" "" "" { Schematic "e:/ywh/quartusii/scanwave/test.bdf" { { 512 32 200 528 "CLK" "" } { 336 280 312 352 "CLK" "" } { 352 960 984 368 "CLK" "" } { 368 960 984 384 "CLK" "" } { 504 200 264 520 "CLK" "" } { 272 616 656 288 "CLK" "" } { 816 200 240 832 "CLK" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.541 ns) + CELL(0.711 ns) 2.721 ns BUS_1:inst9\|RAMTMP7\[0\] 2 REG LC_X24_Y4_N9 3 " "Info: 2: + IC(0.541 ns) + CELL(0.711 ns) = 2.721 ns; Loc. = LC_X24_Y4_N9; Fanout = 3; REG Node = 'BUS_1:inst9\|RAMTMP7\[0\]'" {  } { { "e:/ywh/quartusii/scanwave/db/TEST_cmp.qrpt" "" "" { Report "e:/ywh/quartusii/scanwave/db/TEST_cmp.qrpt" Compiler "TEST" "UNKNOWN" "V1" "e:/ywh/quartusii/scanwave/db/TEST.quartus_db" { Floorplan "" "" "1.252 ns" { CLK BUS_1:inst9|RAMTMP7[0] } "NODE_NAME" } } } { "e:/ywh/quartusii/scanwave/BUS_1.vhd" "" "" { Text "e:/ywh/quartusii/scanwave/BUS_1.vhd" 56 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns 80.12 % " "Info: Total cell delay = 2.180 ns ( 80.12 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.541 ns 19.88 % " "Info: Total interconnect delay = 0.541 ns ( 19.88 % )" {  } {  } 0}  } { { "e:/ywh/quartusii/scanwave/db/TEST_cmp.qrpt" "" "" { Report "e:/ywh/quartusii/scanwave/db/TEST_cmp.qrpt" Compiler "TEST" "UNKNOWN" "V1" "e:/ywh/quartusii/scanwave/db/TEST.quartus_db" { Floorplan "" "" "2.721 ns" { CLK BUS_1:inst9|RAMTMP7[0] } "NODE_NAME" } } }  } 0}  } { { "e:/ywh/quartusii/scanwave/db/TEST_cmp.qrpt" "" "" { Report "e:/ywh/quartusii/scanwave/db/TEST_cmp.qrpt" Compiler "TEST" "UNKNOWN" "V1" "e:/ywh/quartusii/scanwave/db/TEST.quartus_db" { Floorplan "" "" "2.721 ns" { CLK AD_SRAM:inst2|WR } "NODE_NAME" } } } { "e:/ywh/quartusii/scanwave/db/TEST_cmp.qrpt" "" "" { Report "e:/ywh/quartusii/scanwave/db/TEST_cmp.qrpt" Compiler "TEST" "UNKNOWN" "V1" "e:/ywh/quartusii/scanwave/db/TEST.quartus_db" { Floorplan "" "" "2.721 ns" { CLK BUS_1:inst9|RAMTMP7[0] } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "e:/ywh/quartusii/scanwave/BUS_1.vhd" "" "" { Text "e:/ywh/quartusii/scanwave/BUS_1.vhd" 56 -1 0 } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" {  } { { "E:/ywh/QUARTUSII/scanwave/AD_SRAM.vhd" "" "" { Text "E:/ywh/QUARTUSII/scanwave/AD_SRAM.vhd" 24 -1 0 } }  } 0} { "Info" "ITDB_INVERTED_CLOCK_FOUND" "" "Info: Delay path is controlled by inverted clocks -- if clock duty cycle is 50, fmax is divided by two" {  } { { "e:/ywh/quartusii/scanwave/BUS_1.vhd" "" "" { Text "e:/ywh/quartusii/scanwave/BUS_1.vhd" 56 -1 0 } } { "E:/ywh/QUARTUSII/scanwave/AD_SRAM.vhd" "" "" { Text "E:/ywh/QUARTUSII/scanwave/AD_SRAM.vhd" 24 -1 0 } }  } 0}  } { { "e:/ywh/quartusii/scanwave/db/TEST_cmp.qrpt" "" "" { Report "e:/ywh/quartusii/scanwave/db/TEST_cmp.qrpt" Compiler "TEST" "UNKNOWN" "V1" "e:/ywh/quartusii/scanwave/db/TEST.quartus_db" { Floorplan "" "" "5.097 ns" { BUS_1:inst9|RAMTMP7[0] CONV_SINGLE:inst5|LessThan~1COUT0 CONV_SINGLE:inst5|LessThan~2COUT0 CONV_SINGLE:inst5|LessThan~3COUT0 CONV_SINGLE:inst5|LessThan~4COUT0 CONV_SINGLE:inst5|LessThan~5 CONV_SINGLE:inst5|LessThan~8 CONV_SINGLE:inst5|process0~0 AD_SRAM:inst2|WR~0 AD_SRAM:inst2|WR } "NODE_NAME" } } } { "e:/ywh/quartusii/scanwave/db/TEST_cmp.qrpt" "" "" { Report "e:/ywh/quartusii/scanwave/db/TEST_cmp.qrpt" Compiler "TEST" "UNKNOWN" "V1" "e:/ywh/quartusii/scanwave/db/TEST.quartus_db" { Floorplan "" "" "2.721 ns" { CLK AD_SRAM:inst2|WR } "NODE_NAME" } } } { "e:/ywh/quartusii/scanwave/db/TEST_cmp.qrpt" "" "" { Report "e:/ywh/quartusii/scanwave/db/TEST_cmp.qrpt" Compiler "TEST" "UNKNOWN" "V1" "e:/ywh/quartusii/scanwave/db/TEST.quartus_db" { Floorplan "" "" "2.721 ns" { CLK BUS_1:inst9|RAMTMP7[0] } "NODE_NAME" } } }  } 0}
{ "Info" "ITAN_NO_REG2REG_EXIST" "ALE " "Info: No valid register-to-register paths exist for clock ALE" {  } {  } 0}