scanwave.tan.qmsg

数字示波器的FPGA实现 VHDL编写 Quartus7.1测试通过

{ "Info" "ITDB_FULL_TCO_RESULT" "CLK DAYOUT\[1\] generator_accB:inst4\|TEMP 17.376 ns register " "Info: tco from clock \"CLK\" to destination pin \"DAYOUT\[1\]\" through register \"generator_accB:inst4\|TEMP\" is 17.376 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK source 9.038 ns + Longest register " "Info: + Longest clock path from clock \"CLK\" to source register is 9.038 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns CLK 1 CLK PIN_16 354 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_16; Fanout = 354; CLK Node = 'CLK'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLK } "NODE_NAME" } } { "SCANWAVE.bdf" "" { Schematic "I:/数字存储示波器/scanwave/SCANWAVE.bdf" { { 520 16 184 536 "CLK" "" } { 392 1080 1104 408 "CLK" "" } { 408 1080 1104 424 "CLK" "" } { 800 192 232 816 "CLK" "" } { 512 184 224 528 "CLK" "" } { 16 616 656 32 "CLK" "" } { 296 624 648 312 "CLK" "" } { 112 1080 1104 128 "CLK" "" } { 128 1080 1104 144 "CLK" "" } { 344 272 304 360 "CLK" "" } { 848 -184 -136 864 "CLK" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.560 ns) + CELL(0.935 ns) 2.964 ns FREDEVIDER8:inst8\|CLK 2 REG LC_X9_Y6_N2 33 " "Info: 2: + IC(0.560 ns) + CELL(0.935 ns) = 2.964 ns; Loc. = LC_X9_Y6_N2; Fanout = 33; REG Node = 'FREDEVIDER8:inst8\|CLK'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.495 ns" { CLK FREDEVIDER8:inst8|CLK } "NODE_NAME" } } { "fredevider8.vhd" "" { Text "I:/数字存储示波器/scanwave/fredevider8.vhd" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(5.363 ns) + CELL(0.711 ns) 9.038 ns generator_accB:inst4\|TEMP 3 REG LC_X18_Y5_N0 2 " "Info: 3: + IC(5.363 ns) + CELL(0.711 ns) = 9.038 ns; Loc. = LC_X18_Y5_N0; Fanout = 2; REG Node = 'generator_accB:inst4\|TEMP'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "6.074 ns" { FREDEVIDER8:inst8|CLK generator_accB:inst4|TEMP } "NODE_NAME" } } { "generator_accb.vhd" "" { Text "I:/数字存储示波器/scanwave/generator_accb.vhd" 42 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.115 ns ( 34.47 % ) " "Info: Total cell delay = 3.115 ns ( 34.47 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.923 ns ( 65.53 % ) " "Info: Total interconnect delay = 5.923 ns ( 65.53 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "9.038 ns" { CLK FREDEVIDER8:inst8|CLK generator_accB:inst4|TEMP } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "9.038 ns" { CLK CLK~out0 FREDEVIDER8:inst8|CLK generator_accB:inst4|TEMP } { 0.000ns 0.000ns 0.560ns 5.363ns } { 0.000ns 1.469ns 0.935ns 0.711ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "generator_accb.vhd" "" { Text "I:/数字存储示波器/scanwave/generator_accb.vhd" 42 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "8.114 ns + Longest register pin " "Info: + Longest register to pin delay is 8.114 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns generator_accB:inst4\|TEMP 1 REG LC_X18_Y5_N0 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X18_Y5_N0; Fanout = 2; REG Node = 'generator_accB:inst4\|TEMP'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFl