📄 scanwave.tan.qmsg
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{ "Info" "ITAN_NO_REG2REG_EXIST" "ALE " "Info: No valid register-to-register data paths exist for clock \"ALE\"" { } { } 0 0 "No valid register-to-register data paths exist for clock \"%1!s!\"" 0 0 "" 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT_RESTRICTED" "CLK2 register register FREQ_COUNT:inst6\|COUNT2\[4\] FREQ_COUNT:inst6\|COUNT2\[15\] 275.03 MHz Internal " "Info: Clock \"CLK2\" Internal fmax is restricted to 275.03 MHz between source register \"FREQ_COUNT:inst6\|COUNT2\[4\]\" and destination register \"FREQ_COUNT:inst6\|COUNT2\[15\]\"" { { "Info" "ITDB_CLOCK_TCH_TCL" "1.818 ns 1.818 ns 3.636 ns " "Info: fmax restricted to Clock High delay (1.818 ns) plus Clock Low delay (1.818 ns) : restricted to 3.636 ns. Expand message to see actual delay path." { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "2.491 ns + Longest register register " "Info: + Longest register to register delay is 2.491 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns FREQ_COUNT:inst6\|COUNT2\[4\] 1 REG LC_X23_Y6_N6 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X23_Y6_N6; Fanout = 4; REG Node = 'FREQ_COUNT:inst6\|COUNT2\[4\]'" { } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { FREQ_COUNT:inst6|COUNT2[4] } "NODE_NAME" } } { "freq_count.vhd" "" { Text "I:/数字存储示波器/scanwave/freq_count.vhd" 39 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.523 ns) + CELL(0.575 ns) 1.098 ns FREQ_COUNT:inst6\|COUNT2\[4\]~444COUT1 2 COMB LC_X23_Y6_N6 2 " "Info: 2: + IC(0.523 ns) + CELL(0.575 ns) = 1.098 ns; Loc. = LC_X23_Y6_N6; Fanout = 2; COMB Node = 'FREQ_COUNT:inst6\|COUNT2\[4\]~444COUT1'" { } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.098 ns" { FREQ_COUNT:inst6|COUNT2[4] FREQ_COUNT:inst6|COUNT2[4]~444COUT1 } "NODE_NAME" } } { "freq_count.vhd" "" { Text "I:/数字存储示波器/scanwave/freq_count.vhd" 39 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 1.178 ns FREQ_COUNT:inst6\|COUNT2\[5\]~442COUT1 3 COMB LC_X23_Y6_N7 2 " "Info: 3: + IC(0.000 ns) + CELL(0.080 ns) = 1.178 ns; Loc. = LC_X23_Y6_N7; Fanout = 2; COMB Node = 'FREQ_COUNT:inst6\|COUNT2\[5\]~442COUT1'" { } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { FREQ_COUNT:inst6|COUNT2[4]~444COUT1 FREQ_COUNT:inst6|COUNT2[5]~442COUT1 } "NODE_NAME" } } { "freq_count.vhd" "" { Text "I:/数字存储示波器/scanwave/freq_count.vhd" 39 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 1.258 ns FREQ_COUNT:inst6\|COUNT2\[6\]~440COUT1 4 COMB LC_X23_Y6_N8 2 " "Info: 4: + IC(0.000 ns) + CELL(0.080 ns) = 1.258 ns; Loc. = LC_X23_Y6_N8; Fanout = 2; COMB Node = 'FREQ_COUNT:inst6\|COUNT2\[6\]~440COUT1'" { } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { FREQ_COUNT:inst6|COUNT2[5]~442COUT1 FREQ_COUNT:inst6|COUNT2[6]~440COUT1 } "NODE_NAME" } } { "freq_count.vhd" "" { Text "I:/数字存储示波器/scanwave/freq_count.vhd" 39 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.258 ns) 1.516 ns FREQ_COUNT:inst6\|COUNT2\[7\]~438 5 COMB LC_X23_Y6_N9 6 " "Info: 5: + IC(0.000 ns) + CELL(0.258 ns) = 1.516 ns; Loc. = LC_X23_Y6_N9; Fanout = 6; COMB Node = 'FREQ_COUNT:inst6\|COUNT2\[7\]~438'" { } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.258 ns" { FREQ_COUNT:inst6|COUNT2[6]~440COUT1 FREQ_COUNT:inst6|COUNT2[7]~438 } "NODE_NAME" } } { "freq_count.vhd" "" { Text "I:/数字存储示波器/scanwave/freq_count.vhd" 39 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.136 ns) 1.652 ns FREQ_COUNT:inst6\|COUNT2\[12\]~443 6 COMB LC_X23_Y5_N4 3 " "Info: 6: + IC(0.000 ns) + CELL(0.136 ns) = 1.652 ns; Loc. = LC_X23_Y5_N4; Fanout = 3; COMB Node = 'FREQ_COUNT:inst6\|COUNT2\[12\]~443'" { } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.136 ns" { FREQ_COUNT:inst6|COUNT2[7]~438 FREQ_COUNT:inst6|COUNT2[12]~443 } "NODE_NAME" } } { "freq_count.vhd" "" { Text "I:/数字存储示波器/scanwave/freq_count.vhd" 39 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.839 ns) 2.491 ns FREQ_COUNT:inst6\|COUNT2\[15\] 7 REG LC_X23_Y5_N7 2 " "Info: 7: + IC(0.000 ns) + CELL(0.839 ns) = 2.491 ns; Loc. = LC_X23_Y5_N7; Fanout = 2; REG Node = 'FREQ_COUNT:inst6\|COUNT2\[15\]'" { } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.839 ns" { FREQ_COUNT:inst6|COUNT2[12]~443 FREQ_COUNT:inst6|COUNT2[15] } "NODE_NAME" } } { "freq_count.vhd" "" { Text "I:/数字存储示波器/scanwave/freq_count.vhd" 39 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.968 ns ( 79.00 % ) " "Info: Total cell delay = 1.968 ns ( 79.00 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.523 ns ( 21.00 % ) " "Info: Total interconnect delay = 0.523 ns ( 21.00 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.491 ns" { FREQ_COUNT:inst6|COUNT2[4] FREQ_COUNT:inst6|COUNT2[4]~444COUT1 FREQ_COUNT:inst6|COUNT2[5]~442COUT1 FREQ_COUNT:inst6|COUNT2[6]~440COUT1 FREQ_COUNT:inst6|COUNT2[7]~438 FREQ_COUNT:inst6|COUNT2[12]~443 FREQ_COUNT:inst6|COUNT2[15] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "2.491 ns" { FREQ_COUNT:inst6|COUNT2[4] FREQ_COUNT:inst6|COUNT2[4]~444COUT1 FREQ_COUNT:inst6|COUNT2[5]~442COUT1 FREQ_COUNT:inst6|COUNT2[6]~440COUT1 FREQ_COUNT:inst6|COUNT2[7]~438 FREQ_COUNT:inst6|COUNT2[12]~443 FREQ_COUNT:inst6|COUNT2[15] } { 0.000ns 0.523ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns } { 0.000ns 0.575ns 0.080ns 0.080ns 0.258ns 0.136ns 0.839ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-0.038 ns - Smallest " "Info: - Smallest clock skew is -0.038 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK2 destination 6.898 ns + Shortest register " "Info: + Shortest clock path from clock \"CLK2\" to destination register is 6.898 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.475 ns) 1.475 ns CLK2 1 CLK PIN_52 32 " "Info: 1: + IC(0.000 ns) + CELL(1.475 ns) = 1.475 ns; Loc. = PIN_52; Fanout = 32; CLK Node = 'CLK2'" { } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLK2 } "NODE_NAME" } } { "SCANWAVE.bdf" "" { Schematic "I:/数字存储示波器/scanwave/SCANWAVE.bdf" { { 944 -136 32 960 "CLK2" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(4.712 ns) + CELL(0.711 ns) 6.898 ns FREQ_COUNT:inst6\|COUNT2\[15\] 2 REG LC_X23_Y5_N7 2 " "Info: 2: + IC(4.712 ns) + CELL(0.711 ns) = 6.898 ns; Loc. = LC_X23_Y5_N7; Fanout = 2; REG Node = 'FREQ_COUNT:inst6\|COUNT2\[15\]'" { } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "5.423 ns" { CLK2 FREQ_COUNT:inst6|COUNT2[15] } "NODE_NAME" } } { "freq_count.vhd" "" { Text "I:/数字存储示波器/scanwave/freq_count.vhd" 39 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.186 ns ( 31.69 % ) " "Info: Total cell delay = 2.186 ns ( 31.69 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.712 ns ( 68.31 % ) " "Info: Total interconnect delay = 4.712 ns ( 68.31 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "6.898 ns" { CLK2 FREQ_COUNT:inst6|COUNT2[15] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "6.898 ns" { CLK2 CLK2~out0 FREQ_COUNT:inst6|COUNT2[15] } { 0.000ns 0.000ns 4.712ns } { 0.000ns 1.475ns 0.711ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK2 source 6.936 ns - Longest register " "Info: - Longest clock path from clock \"CLK2\" to source register is 6.936 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.475 ns) 1.475 ns CLK2 1 CLK PIN_52 32 " "Info: 1: + IC(0.000 ns) + CELL(1.475 ns) = 1.475 ns; Loc. = PIN_52; Fanout = 32; CLK Node = 'CLK2'" { } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLK2 } "NODE_NAME" } } { "SCANWAVE.bdf" "" { Schematic "I:/数字存储示波器/scanwave/SCANWAVE.bdf" { { 944 -136 32 960 "CLK2" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(4.750 ns) + CELL(0.711 ns) 6.936 ns FREQ_COUNT:inst6\|COUNT2\[4\] 2 REG LC_X23_Y6_N6 4 " "Info: 2: + IC(4.750 ns) + CELL(0.711 ns) = 6.936 ns; Loc. = LC_X23_Y6_N6; Fanout = 4; REG Node = 'FREQ_COUNT:inst6\|COUNT2\[4\]'" { } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "5.461 ns" { CLK2 FREQ_COUNT:inst6|COUNT2[4] } "NODE_NAME" } } { "freq_count.vhd" "" { Text "I:/数字存储示波器/scanwave/freq_count.vhd" 39 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.186 ns ( 31.52 % ) " "Info: Total cell delay = 2.186 ns ( 31.52 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.750 ns ( 68.48 % ) " "Info: Total interconnect delay = 4.750 ns ( 68.48 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "6.936 ns" { CLK2 FREQ_COUNT:inst6|COUNT2[4] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "6.936 ns" { CLK2 CLK2~out0 FREQ_COUNT:inst6|COUNT2[4] } { 0.000ns 0.000ns 4.750ns } { 0.000ns 1.475ns 0.711ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "6.898 ns" { CLK2 FREQ_COUNT:inst6|COUNT2[15] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "6.898 ns" { CLK2 CLK2~out0 FREQ_COUNT:inst6|COUNT2[15] } { 0.000ns 0.000ns 4.712ns } { 0.000ns 1.475ns 0.711ns } "" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "6.936 ns" { CLK2 FREQ_COUNT:inst6|COUNT2[4] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "6.936 ns" { CLK2 CLK2~out0 FREQ_COUNT:inst6|COUNT2[4] } { 0.000ns 0.000ns 4.750ns } { 0.000ns 1.475ns 0.711ns } "" } } } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" { } { { "freq_count.vhd" "" { Text "I:/数字存储示波器/scanwave/freq_count.vhd" 39 -1 0 } } } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" { } { { "freq_count.vhd" "" { Text "I:/数字存储示波器/scanwave/freq_count.vhd" 39 -1 0 } } } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0} } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.491 ns" { FREQ_COUNT:inst6|COUNT2[4] FREQ_COUNT:inst6|COUNT2[4]~444COUT1 FREQ_COUNT:inst6|COUNT2[5]~442COUT1 FREQ_COUNT:inst6|COUNT2[6]~440COUT1 FREQ_COUNT:inst6|COUNT2[7]~438 FREQ_COUNT:inst6|COUNT2[12]~443 FREQ_COUNT:inst6|COUNT2[15] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "2.491 ns" { FREQ_COUNT:inst6|COUNT2[4] FREQ_COUNT:inst6|COUNT2[4]~444COUT1 FREQ_COUNT:inst6|COUNT2[5]~442COUT1 FREQ_COUNT:inst6|COUNT2[6]~440COUT1 FREQ_COUNT:inst6|COUNT2[7]~438 FREQ_COUNT:inst6|COUNT2[12]~443 FREQ_COUNT:inst6|COUNT2[15] } { 0.000ns 0.523ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns } { 0.000ns 0.575ns 0.080ns 0.080ns 0.258ns 0.136ns 0.839ns } "" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "6.898 ns" { CLK2 FREQ_COUNT:inst6|COUNT2[15] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "6.898 ns" { CLK2 CLK2~out0 FREQ_COUNT:inst6|COUNT2[15] } { 0.000ns 0.000ns 4.712ns } { 0.000ns 1.475ns 0.711ns } "" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "6.936 ns" { CLK2 FREQ_COUNT:inst6|COUNT2[4] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "6.936 ns" { CLK2 CLK2~out0 FREQ_COUNT:inst6|COUNT2[4] } { 0.000ns 0.000ns 4.750ns } { 0.000ns 1.475ns 0.711ns } "" } } } 0 0 "fmax restricted to Clock High delay (%1!s!) plus Clock Low delay (%2!s!) : restricted to %3!s!. Expand message to see actual delay path." 0 0 "" 0} } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { FREQ_COUNT:inst6|COUNT2[15] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { FREQ_COUNT:inst6|COUNT2[15] } { } { } "" } } { "freq_count.vhd" "" { Text "I:/数字存储示波器/scanwave/freq_count.vhd" 39 -1 0 } } } 0 0 "Clock \"%1!s!\" %7!s! fmax is restricted to %6!s! between source %2!s! \"%4!s!\" and destination %3!s! \"%5!s!\"" 0 0 "" 0}
{ "Warning" "WTAN_CLOCK_WILL_NOT_OPERATE" "CLK 201 " "Warning: Circuit may not operate. Detected 201 non-operational path(s) clocked by clock \"CLK\" with clock skew larger than data delay. See Compilation Report for details." { } { } 0 0 "Circuit may not operate. Detected %2!d! non-operational path(s) clocked by clock \"%1!s!\" with clock skew larger than data delay. See Compilation Report for details." 0 0 "" 0}
{ "Info" "ITDB_FULL_NEGATIVE_HOLD_RESULT" "BUS_1:inst5\|RAMTMP5\[7\] VOLTAGE_CONV:inst17\|TEMP\[7\] CLK 4.587 ns " "Info: Found hold time violation between source pin or register \"BUS_1:inst5\|RAMTMP5\[7\]\" and destination pin or register \"VOLTAGE_CONV:inst17\|TEMP\[7\]\" for clock \"CLK\" (Hold time is 4.587 ns)" { { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "5.909 ns + Largest " "Info: + Largest clock skew is 5.909 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK destination 8.691 ns + Longest register " "Info: + Longest clock path from clock \"CLK\" to destination register is 8.691 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns CLK 1 CLK PIN_16 354 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_16; Fanout = 354; CLK Node = 'CLK'" { } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLK } "NODE_NAME" } } { "SCANWAVE.bdf" "" { Schematic "I:/数字存储示波器/scanwave/SCANWAVE.bdf" { { 520 16 184 536 "CLK" "" } { 392 1080 1104 408 "CLK" "" } { 408 1080 1104 424 "CLK" "" } { 800 192 232 816 "CLK" "" } { 512 184 224 528 "CLK" "" } { 16 616 656 32 "CLK" "" } { 296 624 648 312 "CLK" "" } { 112 1080 1104 128 "CLK" "" } { 128 1080 1104 144 "CLK" "" } { 344 272 304 360 "CLK" "" } { 848 -184 -136 864 "CLK" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.560 ns) + CELL(0.935 ns) 2.964 ns MAX114:inst11\|RD 2 REG LC_X8_Y6_N1 6 " "Info: 2: + IC(0.560 ns) + CELL(0.935 ns) = 2.964 ns; Loc. = LC_X8_Y6_N1; Fanout = 6; REG Node = 'MAX114:inst11\|RD'" { } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.495 ns" { CLK MAX114:inst11|RD } "NODE_NAME" } } { "max114.vhd" "" { Text "I:/数字存储示波器/scanwave/max114.vhd" 22 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.582 ns) + CELL(0.935 ns) 4.481 ns FREDEVIDER2:inst13\|CLK 3 REG LC_X8_Y6_N6 65 " "Info: 3: + IC(0.582 ns) + CELL(0.935 ns) = 4.481 ns; Loc. = LC_X8_Y6_N6; Fanout = 65; REG Node = 'FREDEVIDER2:inst13\|CLK'" { } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.517 ns" { MAX114:inst11|RD FREDEVIDER2:inst13|CLK } "NODE_NAME" } } { "fredevider2.vhd" "" { Text "I:/数字存储示波器/scanwave/fredevider2.vhd" 15 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(3.499 ns) + CELL(0.711 ns) 8.691 ns VOLTAGE_CONV:inst17\|TEMP\[7\] 4 REG LC_X17_Y7_N7 1 " "Info: 4: + IC(3.499 ns) + CELL(0.711 ns) = 8.691 ns; Loc. = LC_X17_Y7_N7; Fanout = 1; REG Node = 'VOLTAGE_CONV:inst17\|TEMP\[7\]'" { } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "4.210 ns" { FREDEVIDER2:inst13|CLK VOLTAGE_CONV:inst17|TEMP[7] } "NODE_NAME" } } { "VOLTAGE_CONV.vhd" "" { Text "I:/数字存储示波器/scanwave/VOLTAGE_CONV.vhd" 38 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.050 ns ( 46.60 % ) " "Info: Total cell delay = 4.050 ns ( 46.60 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.641 ns ( 53.40 % ) " "Info: Total interconnect delay = 4.641 ns ( 53.40 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "8.691 ns" { CLK MAX114:inst11|RD FREDEVIDER2:inst13|CLK VOLTAGE_CONV:inst17|TEMP[7] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "8.691 ns" { CLK CLK~out0 MAX114:inst11|RD FREDEVIDER2:inst13|CLK VOLTAGE_CONV:inst17|TEMP[7] } { 0.000ns 0.000ns 0.560ns 0.582ns 3.499ns } { 0.000ns 1.469ns 0.935ns 0.935ns 0.711ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK source 2.782 ns - Shortest register " "Info: - Shortest clock path from clock \"CLK\" to source register is 2.782 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns CLK 1 CLK PIN_16 354 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_16; Fanout = 354; CLK Node = 'CLK'" { } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLK } "NODE_NAME" } } { "SCANWAVE.bdf" "" { Schematic "I:/数字存储示波器/scanwave/SCANWAVE.bdf" { { 520 16 184 536 "CLK" "" } { 392 1080 1104 408 "CLK" "" } { 408 1080 1104 424 "CLK" "" } { 800 192 232 816 "CLK" "" } { 512 184 224 528 "CLK" "" } { 16 616 656 32 "CLK" "" } { 296 624 648 312 "CLK" "" } { 112 1080 1104 128 "CLK" "" } { 128 1080 1104 144 "CLK" "" } { 344 272 304 360 "CLK" "" } { 848 -184 -136 864 "CLK" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.602 ns) + CELL(0.711 ns) 2.782 ns BUS_1:inst5\|RAMTMP5\[7\] 2 REG LC_X17_Y7_N8 2 " "Info: 2: + IC(0.602 ns) + CELL(0.711 ns) = 2.782 ns; Loc. = LC_X17_Y7_N8; Fanout = 2; REG Node = 'BUS_1:inst5\|RAMTMP5\[7\]'" { } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.313 ns" { CLK BUS_1:inst5|RAMTMP5[7] } "NODE_NAME" } } { "BUS_1.vhd" "" { Text "I:/数字存储示波器/scanwave/BUS_1.vhd" 64 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 78.36 % ) " "Info: Total cell delay = 2.180 ns ( 78.36 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.602 ns ( 21.64 % ) " "Info: Total interconnect delay = 0.602 ns ( 21.64 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.782 ns" { CLK BUS_1:inst5|RAMTMP5[7] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "2.782 ns" { CLK CLK~out0 BUS_1:inst5|RAMTMP5[7] } { 0.000ns 0.000ns 0.602ns } { 0.000ns 1.469ns 0.711ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "8.691 ns" { CLK MAX114:inst11|RD FREDEVIDER2:inst13|CLK VOLTAGE_CONV:inst17|TEMP[7] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "8.691 ns" { CLK CLK~out0 MAX114:inst11|RD FREDEVIDER2:inst13|CLK VOLTAGE_CONV:inst17|TEMP[7] } { 0.000ns 0.000ns 0.560ns 0.582ns 3.499ns } { 0.000ns 1.469ns 0.935ns 0.935ns 0.711ns } "" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.782 ns" { CLK BUS_1:inst5|RAMTMP5[7] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "2.782 ns" { CLK CLK~out0 BUS_1:inst5|RAMTMP5[7] } { 0.000ns 0.000ns 0.602ns } { 0.000ns 1.469ns 0.711ns } "" } } } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns - " "Info: - Micro clock to output delay of source is 0.224 ns" { } { { "BUS_1.vhd" "" { Text "I:/数字存储示波器/scanwave/BUS_1.vhd" 64 -1 0 } } } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "1.113 ns - Shortest register register " "Info: - Shortest register to register delay is 1.113 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns BUS_1:inst5\|RAMTMP5\[7\] 1 REG LC_X17_Y7_N8 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X17_Y7_N8; Fanout = 2; REG Node = 'BUS_1:inst5\|RAMTMP5\[7\]'" { } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { BUS_1:inst5|RAMTMP5[7] } "NODE_NAME" } } { "BUS_1.vhd" "" { Text "I:/数字存储示波器/scanwave/BUS_1.vhd" 64 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.506 ns) + CELL(0.607 ns) 1.113 ns VOLTAGE_CONV:inst17\|TEMP\[7\] 2 REG LC_X17_Y7_N7 1 " "Info: 2: + IC(0.506 ns) + CELL(0.607 ns) = 1.113 ns; Loc. = LC_X17_Y7_N7; Fanout = 1; REG Node = 'VOLTAGE_CONV:inst17\|TEMP\[7\]'" { } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.113 ns" { BUS_1:inst5|RAMTMP5[7] VOLTAGE_CONV:inst17|TEMP[7] } "NODE_NAME" } } { "VOLTAGE_CONV.vhd" "" { Text "I:/数字存储示波器/scanwave/VOLTAGE_CONV.vhd" 38 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.607 ns ( 54.54 % ) " "Info: Total cell delay = 0.607 ns ( 54.54 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.506 ns ( 45.46 % ) " "Info: Total interconnect delay = 0.506 ns ( 45.46 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.113 ns" { BUS_1:inst5|RAMTMP5[7] VOLTAGE_CONV:inst17|TEMP[7] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "1.113 ns" { BUS_1:inst5|RAMTMP5[7] VOLTAGE_CONV:inst17|TEMP[7] } { 0.000ns 0.506ns } { 0.000ns 0.607ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TH_DELAY" "0.015 ns + " "Info: + Micro hold delay of destination is 0.015 ns" { } { { "VOLTAGE_CONV.vhd" "" { Text "I:/数字存储示波器/scanwave/VOLTAGE_CONV.vhd" 38 -1 0 } } } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0 "" 0} } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "8.691 ns" { CLK MAX114:inst11|RD FREDEVIDER2:inst13|CLK VOLTAGE_CONV:inst17|TEMP[7] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "8.691 ns" { CLK CLK~out0 MAX114:inst11|RD FREDEVIDER2:inst13|CLK VOLTAGE_CONV:inst17|TEMP[7] } { 0.000ns 0.000ns 0.560ns 0.582ns 3.499ns } { 0.000ns 1.469ns 0.935ns 0.935ns 0.711ns } "" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.782 ns" { CLK BUS_1:inst5|RAMTMP5[7] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "2.782 ns" { CLK CLK~out0 BUS_1:inst5|RAMTMP5[7] } { 0.000ns 0.000ns 0.602ns } { 0.000ns 1.469ns 0.711ns } "" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.113 ns" { BUS_1:inst5|RAMTMP5[7] VOLTAGE_CONV:inst17|TEMP[7] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "1.113 ns" { BUS_1:inst5|RAMTMP5[7] VOLTAGE_CONV:inst17|TEMP[7] } { 0.000ns 0.506ns } { 0.000ns 0.607ns } "" } } } 0 0 "Found hold time violation between source pin or register \"%1!s!\" and destination pin or register \"%2!s!\" for clock \"%3!s!\" (Hold time is %4!s!)" 0 0 "" 0}
{ "Info" "ITDB_TSU_RESULT" "BUS_1:inst5\|RAMTMP5\[7\] WR CLK 11.499 ns register " "Info: tsu for register \"BUS_1:inst5\|RAMTMP5\[7\]\" (data pin = \"WR\", clock pin = \"CLK\") is 11.499 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "14.244 ns + Longest pin register " "Info: + Longest pin to register delay is 14.244 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns WR 1 PIN PIN_77 5 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_77; Fanout = 5; PIN Node = 'WR'" { } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { WR } "NODE_NAME" } } { "SCANWAVE.bdf" "" { Schematic "I:/数字存储示波器/scanwave/SCANWAVE.bdf" { { 792 16 184 808 "WR" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(5.824 ns) + CELL(0.590 ns) 7.883 ns BUS_1:inst5\|RAMTMP7\[7\]~114 2 COMB LC_X21_Y7_N1 3 " "Info: 2: + IC(5.824 ns) + CELL(0.590 ns) = 7.883 ns; Loc. = LC_X21_Y7_N1; Fanout = 3; COMB Node = 'BUS_1:inst5\|RAMTMP7\[7\]~114'" { } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "6.414 ns" { WR BUS_1:inst5|RAMTMP7[7]~114 } "NODE_NAME" } } { "BUS_1.vhd" "" { Text "I:/数字存储示波器/scanwave/BUS_1.vhd" 64 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.482 ns) + CELL(0.590 ns) 10.955 ns BUS_1:inst5\|RAMTMP5\[7\]~156 3 COMB LC_X11_Y6_N8 8 " "Info: 3: + IC(2.482 ns) + CELL(0.590 ns) = 10.955 ns; Loc. = LC_X11_Y6_N8; Fanout = 8; COMB Node = 'BUS_1:inst5\|RAMTMP5\[7\]~156'" { } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "3.072 ns" { BUS_1:inst5|RAMTMP7[7]~114 BUS_1:inst5|RAMTMP5[7]~156 } "NODE_NAME" } } { "BUS_1.vhd" "" { Text "I:/数字存储示波器/scanwave/BUS_1.vhd" 64 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.422 ns) + CELL(0.867 ns) 14.244 ns BUS_1:inst5\|RAMTMP5\[7\] 4 REG LC_X17_Y7_N8 2 " "Info: 4: + IC(2.422 ns) + CELL(0.867 ns) = 14.244 ns; Loc. = LC_X17_Y7_N8; Fanout = 2; REG Node = 'BUS_1:inst5\|RAMTMP5\[7\]'" { } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "3.289 ns" { BUS_1:inst5|RAMTMP5[7]~156 BUS_1:inst5|RAMTMP5[7] } "NODE_NAME" } } { "BUS_1.vhd" "" { Text "I:/数字存储示波器/scanwave/BUS_1.vhd" 64 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.516 ns ( 24.68 % ) " "Info: Total cell delay = 3.516 ns ( 24.68 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "10.728 ns ( 75.32 % ) " "Info: Total interconnect delay = 10.728 ns ( 75.32 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "14.244 ns" { WR BUS_1:inst5|RAMTMP7[7]~114 BUS_1:inst5|RAMTMP5[7]~156 BUS_1:inst5|RAMTMP5[7] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "14.244 ns" { WR WR~out0 BUS_1:inst5|RAMTMP7[7]~114 BUS_1:inst5|RAMTMP5[7]~156 BUS_1:inst5|RAMTMP5[7] } { 0.000ns 0.000ns 5.824ns 2.482ns 2.422ns } { 0.000ns 1.469ns 0.590ns 0.590ns 0.867ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" { } { { "BUS_1.vhd" "" { Text "I:/数字存储示波器/scanwave/BUS_1.vhd" 64 -1 0 } } } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK destination 2.782 ns - Shortest register " "Info: - Shortest clock path from clock \"CLK\" to destination register is 2.782 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns CLK 1 CLK PIN_16 354 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_16; Fanout = 354; CLK Node = 'CLK'" { } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLK } "NODE_NAME" } } { "SCANWAVE.bdf" "" { Schematic "I:/数字存储示波器/scanwave/SCANWAVE.bdf" { { 520 16 184 536 "CLK" "" } { 392 1080 1104 408 "CLK" "" } { 408 1080 1104 424 "CLK" "" } { 800 192 232 816 "CLK" "" } { 512 184 224 528 "CLK" "" } { 16 616 656 32 "CLK" "" } { 296 624 648 312 "CLK" "" } { 112 1080 1104 128 "CLK" "" } { 128 1080 1104 144 "CLK" "" } { 344 272 304 360 "CLK" "" } { 848 -184 -136 864 "CLK" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.602 ns) + CELL(0.711 ns) 2.782 ns BUS_1:inst5\|RAMTMP5\[7\] 2 REG LC_X17_Y7_N8 2 " "Info: 2: + IC(0.602 ns) + CELL(0.711 ns) = 2.782 ns; Loc. = LC_X17_Y7_N8; Fanout = 2; REG Node = 'BUS_1:inst5\|RAMTMP5\[7\]'" { } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.313 ns" { CLK BUS_1:inst5|RAMTMP5[7] } "NODE_NAME" } } { "BUS_1.vhd" "" { Text "I:/数字存储示波器/scanwave/BUS_1.vhd" 64 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 78.36 % ) " "Info: Total cell delay = 2.180 ns ( 78.36 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.602 ns ( 21.64 % ) " "Info: Total interconnect delay = 0.602 ns ( 21.64 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.782 ns" { CLK BUS_1:inst5|RAMTMP5[7] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "2.782 ns" { CLK CLK~out0 BUS_1:inst5|RAMTMP5[7] } { 0.000ns 0.000ns 0.602ns } { 0.000ns 1.469ns 0.711ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "14.244 ns" { WR BUS_1:inst5|RAMTMP7[7]~114 BUS_1:inst5|RAMTMP5[7]~156 BUS_1:inst5|RAMTMP5[7] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "14.244 ns" { WR WR~out0 BUS_1:inst5|RAMTMP7[7]~114 BUS_1:inst5|RAMTMP5[7]~156 BUS_1:inst5|RAMTMP5[7] } { 0.000ns 0.000ns 5.824ns 2.482ns 2.422ns } { 0.000ns 1.469ns 0.590ns 0.590ns 0.867ns } "" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.782 ns" { CLK BUS_1:inst5|RAMTMP5[7] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "2.782 ns" { CLK CLK~out0 BUS_1:inst5|RAMTMP5[7] } { 0.000ns 0.000ns 0.602ns } { 0.000ns 1.469ns 0.711ns } "" } } } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0}
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