scanwave.tan.qmsg

数字示波器的FPGA实现 VHDL编写 Quartus7.1测试通过

{ "Warning" "WTAN_SCC_LOOP" "1 " "Warning: Found combinational loop of 1 nodes" { { "Warning" "WTAN_SCC_NODE" "CONV_SINGLE:inst22\|TEMP\[6\] " "Warning: Node \"CONV_SINGLE:inst22\|TEMP\[6\]\"" {  } { { "CONV_SINGLE.vhd" "" { Text "I:/数字存储示波器/scanwave/CONV_SINGLE.vhd" 22 -1 0 } }  } 0 0 "Node \"%1!s!\"" 0 0 "" 0}  } { { "CONV_SINGLE.vhd" "" { Text "I:/数字存储示波器/scanwave/CONV_SINGLE.vhd" 22 -1 0 } }  } 0 0 "Found combinational loop of %1!d! nodes" 0 0 "" 0}
{ "Warning" "WTAN_SCC_LOOP" "1 " "Warning: Found combinational loop of 1 nodes" { { "Warning" "WTAN_SCC_NODE" "CONV_SINGLE:inst22\|TEMP\[5\] " "Warning: Node \"CONV_SINGLE:inst22\|TEMP\[5\]\"" {  } { { "CONV_SINGLE.vhd" "" { Text "I:/数字存储示波器/scanwave/CONV_SINGLE.vhd" 22 -1 0 } }  } 0 0 "Node \"%1!s!\"" 0 0 "" 0}  } { { "CONV_SINGLE.vhd" "" { Text "I:/数字存储示波器/scanwave/CONV_SINGLE.vhd" 22 -1 0 } }  } 0 0 "Found combinational loop of %1!d! nodes" 0 0 "" 0}
{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "CLK " "Info: Assuming node \"CLK\" is an undefined clock" {  } { { "SCANWAVE.bdf" "" { Schematic "I:/数字存储示波器/scanwave/SCANWAVE.bdf" { { 520 16 184 536 "CLK" "" } { 392 1080 1104 408 "CLK" "" } { 408 1080 1104 424 "CLK" "" } { 800 192 232 816 "CLK" "" } { 512 184 224 528 "CLK" "" } { 16 616 656 32 "CLK" "" } { 296 624 648 312 "CLK" "" } { 112 1080 1104 128 "CLK" "" } { 128 1080 1104 144 "CLK" "" } { 344 272 304 360 "CLK" "" } { 848 -184 -136 864 "CLK" "" } } } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "CLK" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0 "" 0} { "Info" "ITAN_NODE_MAP_TO_CLK" "ALE " "Info: Assuming node \"ALE\" is an undefined clock" {  } { { "SCANWAVE.bdf" "" { Schematic "I:/数字存储示波器/scanwave/SCANWAVE.bdf" { { 760 16 184 776 "ALE" "" } } } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "ALE" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0 "" 0} { "Info" "ITAN_NODE_MAP_TO_CLK" "CLK2 " "Info: Assuming node \"CLK2\" is an undefined clock" {  } { { "SCANWAVE.bdf" "" { Schematic "I:/数字存储示波器/scanwave/SCANWAVE.bdf" { { 944 -136 32 960 "CLK2" "" } } } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "CLK2" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0 "" 0}  } {  } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0 "" 0}
{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "4 " "Warning: Found 4 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_RIPPLE_CLK" "FREDEVIDER10:inst18\|CLK " "Info: Detected ripple clock \"FREDEVIDER10:inst18\|CLK\" as buffer" {  } { { "fredevider10.vhd" "" { Text "I:/数字存储示波器/scanwave/fredevider10.vhd" 17 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "FREDEVIDER10:inst18\|CLK" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "MAX114:inst11\|RD " "Info: Detected ripple clock \"MAX114:inst11\|RD\" as buffer" {  } { { "max114.vhd" "" { Text "I:/数字存储示波器/scanwave/max114.vhd" 22 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "MAX114:inst11\|RD" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "FREDEVIDER8:inst8\|CLK " "Info: Detected ripple clock \"FREDEVIDER8:inst8\|CLK\" as buffer" {  } { { "fredevider8.vhd" "" { Text "I:/数字存储示波器/scanwave/fredevider8.vhd" 17 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "FREDEVIDER8:inst8\|CLK" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "FREDEVIDER2:inst13\|CLK " "Info: Detected ripple clock \"FREDEVIDER2:inst13\|CLK\" as buffer" {  } { { "fredevider2.vhd" "" { Text "I:/数字存储示波器/scanwave/fredevider2.vhd" 15 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "FREDEVIDER2:inst13\|CLK" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0}  } {  } 0 0 "Found %1!d! node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" 0 0 "" 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "CLK register GET_RDADDR:inst10\|COUNTER\[7\] memory dram:inst\|altsyncram:altsyncram_component\|altsyncram_fbg1:auto_generated\|ram_block1a5~portb_address_reg7 56.09 MHz 17.828 ns Internal " "Info: Clock \"CLK\" has Internal fmax of 56.09 MHz between source register \"GET_RDADDR:inst10\|COUNTER\[7\]\" and destination memory \"dram:inst\|altsyncram:altsyncram_component\|altsyncram_fbg1:auto_generated\|ram_block1a5~portb_address_reg7\" (period= 17.828 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "2.710 ns + Longest register memory " "Info: + Longest register to memory delay is 2.710 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns GET_RDADDR:inst10\|COUNTER\[7\] 1 REG LC_X12_Y9_N1 13 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X12_Y9_N1; Fanout = 13; REG Node = 'GET_RDADDR:inst10\|COUNTER\[7\]'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GET_RDADDR:inst10|COUNTER[7] } "NODE_NAME" } } { "GET_RDADDR.VHD" "" { Text "I:/数字存储示波器/scanwave/GET_RDADDR.VHD" 22 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.380 ns) + CELL(0.330 ns) 2.710 ns dram:inst\|altsyncram:altsyncram_component\|altsyncram_fbg1:auto_generated\|ram_block1a5~portb_address_reg7 2 MEM M4K_X13_Y12 2 " "Info: 2: + IC(2.380 ns) + CELL(0.330 ns) = 2.710 ns; Loc. = M4K_X13_Y12; Fanout = 2; MEM Node = 'dram:inst\|altsyncram:altsyncram_component\|altsyncram_fbg1:auto_generated\|ram_block1a5~portb_address_reg7'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.710 ns" { GET_RDADDR:inst10|COUNTER[7] dram:inst|altsyncram:altsyncram_component|altsyncram_fbg1:auto_generated|ram_block1a5~portb_address_reg7 } "NODE_NAME" } } { "db/altsyncram_fbg1.tdf" "" { Text "I:/数字存储示波器/scanwave/db/altsyncram_fbg1.tdf" 197 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.330 ns ( 12.18 % ) " "Info: Total cell delay = 0.330 ns ( 12.18 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.380 ns ( 87.82 % ) " "Info: Total interconnect delay = 2.380 ns ( 87.82 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.710 ns" { GET_RDADDR:inst10|COUNTER[7] dram:inst|altsyncram:altsyncram_component|altsyncram_fbg1:auto_generated|ram_block1a5~portb_address_reg7 } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "2.710 ns" { GET_RDADDR:inst10|COUNTER[7] dram:inst|altsyncram:altsyncram_component|altsyncram_fbg1:auto_generated|ram_block1a5~portb_address_reg7 } { 0.000ns 2.380ns } { 0.000ns 0.330ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-5.887 ns - Smallest " "Info: - Smallest clock skew is -5.887 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK destination 2.789 ns + Shortest memory " "Info: + Shortest clock path from clock \"CLK\" to destination memory is 2.789 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns CLK 1 CLK PIN_16 354 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_16; Fanout = 354; CLK Node = 'CLK'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLK } "NODE_NAME" } } { "SCANWAVE.bdf" "" { Schematic "I:/数字存储示波器/scanwave/SCANWAVE.bdf" { { 520 16 184 536 "CLK" "" } { 392 1080 1104 408 "CLK" "" } { 408 1080 1104 424 "CLK" "" } { 800 192 232 816 "CLK" "" } { 512 184 224 528 "CLK" "" } { 16 616 656 32 "CLK" "" } { 296 624 648 312 "CLK" "" } { 112 1080 1104 128 "CLK" "" } { 128 1080 1104 144 "CLK" "" } { 344 272 304 360 "CLK" "" } { 848 -184 -136 864 "CLK" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.602 ns) + CELL(0.718 ns) 2.789 ns dram:inst\|altsyncram:altsyncram_component\|altsyncram_fbg1:auto_generated\|ram_block1a5~portb_address_reg7 2 MEM M4K_X13_Y12 2 " "Info: 2: + IC(0.602 ns) + CELL(0.718 ns) = 2.789 ns; Loc. = M4K_X13_Y12; Fanout = 2; MEM Node = 'dram:inst\|altsyncram:altsyncram_component\|altsyncram_fbg1:auto_generated\|ram_block1a5~portb_address_reg7'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.320 ns" { CLK dram:inst|altsyncram:altsyncram_component|altsyncram_fbg1:auto_generated|ram_block1a5~portb_address_reg7 } "NODE_NAME" } } { "db/altsyncram_fbg1.tdf" "" { Text "I:/数字存储示波器/scanwave/db/altsyncram_fbg1.tdf" 197 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.187 ns ( 78.42 % ) " "Info: Total cell delay = 2.187 ns ( 78.42 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.602 ns ( 21.58 % ) " "Info: Total interconnect delay = 0.602 ns ( 21.58 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.789 ns" { CLK dram:inst|altsyncram:altsyncram_component|altsyncram_fbg1:auto_generated|ram_block1a5~portb_address_reg7 } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "2.789 ns" { CLK CLK~out0 dram:inst|altsyncram:altsyncram_component|altsyncram_fbg1:auto_generated|ram_block1a5~portb_address_reg7 } { 0.000ns 0.000ns 0.602ns } { 0.000ns 1.469ns 0.718ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK source 8.676 ns - Longest register " "Info: - Longest clock path from clock \"CLK\" to source register is 8.676 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns CLK 1 CLK PIN_16 354 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_16; Fanout = 354; CLK Node = 'CLK'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLK } "NODE_NAME" } } { "SCANWAVE.bdf" "" { Schematic "I:/数字存储示波器/scanwave/SCANWAVE.bdf" { { 520 16 184 536 "CLK" "" } { 392 1080 1104 408 "CLK" "" } { 408 1080 1104 424 "CLK" "" } { 800 192 232 816 "CLK" "" } { 512 184 224 528 "CLK" "" } { 16 616 656 32 "CLK" "" } { 296 624 648 312 "CLK" "" } { 112 1080 1104 128 "CLK" "" } { 128 1080 1104 144 "CLK" "" } { 344 272 304 360 "CLK" "" } { 848 -184 -136 864 "CLK" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.560 ns) + CELL(0.935 ns) 2.964 ns MAX114:inst11\|RD 2 REG LC_X8_Y6_N1 6 " "Info: 2: + IC(0.560 ns) + CELL(0.935 ns) = 2.964 ns; Loc. = LC_X8_Y6_N1; Fanout = 6; REG Node = 'MAX114:inst11\|RD'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.495 ns" { CLK MAX114:inst11|RD } "NODE_NAME" } } { "max114.vhd" "" { Text "I:/数字存储示波器/scanwave/max114.vhd" 22 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.582 ns) + CELL(0.935 ns) 4.481 ns FREDEVIDER2:inst13\|CLK 3 REG LC_X8_Y6_N6 65 " "Info: 3: + IC(0.582 ns) + CELL(0.935 ns) = 4.481 ns; Loc. = LC_X8_Y6_N6; Fanout = 65; REG Node = 'FREDEVIDER2:inst13\|CLK'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.517 ns" { MAX114:inst11|RD FREDEVIDER2:inst13|CLK } "NODE_NAME" } } { "fredevider2.vhd" "" { Text "I:/数字存储示波器/scanwave/fredevider2.vhd" 15 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(3.484 ns) + CELL(0.711 ns) 8.676 ns GET_RDADDR:inst10\|COUNTER\[7\] 4 REG LC_X12_Y9_N1 13 " "Info: 4: + IC(3.484 ns) + CELL(0.711 ns) = 8.676 ns; Loc. = LC_X12_Y9_N1; Fanout = 13; REG Node = 'GET_RDADDR:inst10\|COUNTER\[7\]'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "4.195 ns" { FREDEVIDER2:inst13|CLK GET_RDADDR:inst10|COUNTER[7] } "NODE_NAME" } } { "GET_RDADDR.VHD" "" { Text "I:/数字存储示波器/scanwave/GET_RDADDR.VHD" 22 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.050 ns ( 46.68 % ) " "Info: Total cell delay = 4.050 ns ( 46.68 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.626 ns ( 53.32 % ) " "Info: Total interconnect delay = 4.626 ns ( 53.32 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "8.676 ns" { CLK MAX114:inst11|RD FREDEVIDER2:inst13|CLK GET_RDADDR:inst10|COUNTER[7] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "8.676 ns" { CLK CLK~out0 MAX114:inst11|RD FREDEVIDER2:inst13|CLK GET_RDADDR:inst10|COUNTER[7] } { 0.000ns 0.000ns 0.560ns 0.582ns 3.484ns } { 0.000ns 1.469ns 0.935ns 0.935ns 0.711ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.789 ns" { CLK dram:inst|altsyncram:altsyncram_component|altsyncram_fbg1:auto_generated|ram_block1a5~portb_address_reg7 } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "2.789 ns" { CLK CLK~out0 dram:inst|altsyncram:altsyncram_component|altsyncram_fbg1:auto_generated|ram_block1a5~portb_address_reg7 } { 0.000ns 0.000ns 0.602ns } { 0.000ns 1.469ns 0.718ns } "" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "8.676 ns" { CLK MAX114:inst11|RD FREDEVIDER2:inst13|CLK GET_RDADDR:inst10|COUNTER[7] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "8.676 ns" { CLK CLK~out0 MAX114:inst11|RD FREDEVIDER2:inst13|CLK GET_RDADDR:inst10|COUNTER[7] } { 0.000ns 0.000ns 0.560ns 0.582ns 3.484ns } { 0.000ns 1.469ns 0.935ns 0.935ns 0.711ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "GET_RDADDR.VHD" "" { Text "I:/数字存储示波器/scanwave/GET_RDADDR.VHD" 22 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.093 ns + " "Info: + Micro setup delay of destination is 0.093 ns" {  } { { "db/altsyncram_fbg1.tdf" "" { Text "I:/数字存储示波器/scanwave/db/altsyncram_fbg1.tdf" 197 2 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_INVERTED_CLOCK_FOUND" "" "Info: Delay path is controlled by inverted clocks -- if clock duty cycle is 50%, fmax is divided by two" {  } { { "GET_RDADDR.VHD" "" { Text "I:/数字存储示波器/scanwave/GET_RDADDR.VHD" 22 -1 0 } } { "db/altsyncram_fbg1.tdf" "" { Text "I:/数字存储示波器/scanwave/db/altsyncram_fbg1.tdf" 197 2 0 } }  } 0 0 "Delay path is controlled by inverted clocks -- if clock duty cycle is 50%, fmax is divided by two" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.710 ns" { GET_RDADDR:inst10|COUNTER[7] dram:inst|altsyncram:altsyncram_component|altsyncram_fbg1:auto_generated|ram_block1a5~portb_address_reg7 } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "2.710 ns" { GET_RDADDR:inst10|COUNTER[7] dram:inst|altsyncram:altsyncram_component|altsyncram_fbg1:auto_generated|ram_block1a5~portb_address_reg7 } { 0.000ns 2.380ns } { 0.000ns 0.330ns } "" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.789 ns" { CLK dram:inst|altsyncram:altsyncram_component|altsyncram_fbg1:auto_generated|ram_block1a5~portb_address_reg7 } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "2.789 ns" { CLK CLK~out0 dram:inst|altsyncram:altsyncram_component|altsyncram_fbg1:auto_generated|ram_block1a5~portb_address_reg7 } { 0.000ns 0.000ns 0.602ns } { 0.000ns 1.469ns 0.718ns } "" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "8.676 ns" { CLK MAX114:inst11|RD FREDEVIDER2:inst13|CLK GET_RDADDR:inst10|COUNTER[7] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "8.676 ns" { CLK CLK~out0 MAX114:inst11|RD FREDEVIDER2:inst13|CLK GET_RDADDR:inst10|COUNTER[7] } { 0.000ns 0.000ns 0.560ns 0.582ns 3.484ns } { 0.000ns 1.469ns 0.935ns 0.935ns 0.711ns } "" } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0 "" 0}