scanwave.hier_info

数字示波器的FPGA实现 VHDL编写 Quartus7.1测试通过

rdaddress[8] => altsyncram:altsyncram_component.address_b[8]
rdaddress[9] => altsyncram:altsyncram_component.address_b[9]
rdaddress[10] => altsyncram:altsyncram_component.address_b[10]
wrclock => altsyncram:altsyncram_component.clock0
rdclock => altsyncram:altsyncram_component.clock1
q[0] <= altsyncram:altsyncram_component.q_b[0]
q[1] <= altsyncram:altsyncram_component.q_b[1]
q[2] <= altsyncram:altsyncram_component.q_b[2]
q[3] <= altsyncram:altsyncram_component.q_b[3]
q[4] <= altsyncram:altsyncram_component.q_b[4]
q[5] <= altsyncram:altsyncram_component.q_b[5]
q[6] <= altsyncram:altsyncram_component.q_b[6]
q[7] <= altsyncram:altsyncram_component.q_b[7]


|SCANWAVE|dram:inst14|altsyncram:altsyncram_component
wren_a => altsyncram_fbg1:auto_generated.wren_a
rden_a => ~NO_FANOUT~
wren_b => ~NO_FANOUT~
rden_b => ~NO_FANOUT~
data_a[0] => altsyncram_fbg1:auto_generated.data_a[0]
data_a[1] => altsyncram_fbg1:auto_generated.data_a[1]
data_a[2] => altsyncram_fbg1:auto_generated.data_a[2]
data_a[3] => altsyncram_fbg1:auto_generated.data_a[3]
data_a[4] => altsyncram_fbg1:auto_generated.data_a[4]
data_a[5] => altsyncram_fbg1:auto_generated.data_a[5]
data_a[6] => altsyncram_fbg1:auto_generated.data_a[6]
data_a[7] => altsyncram_fbg1:auto_generated.data_a[7]
data_b[0] => ~NO_FANOUT~
data_b[1] => ~NO_FANOUT~
data_b[2] => ~NO_FANOUT~
data_b[3] => ~NO_FANOUT~
data_b[4] => ~NO_FANOUT~
data_b[5] => ~NO_FANOUT~
data_b[6] => ~NO_FANOUT~
data_b[7] => ~NO_FANOUT~
address_a[0] => altsyncram_fbg1:auto_generated.address_a[0]
address_a[1] => altsyncram_fbg1:auto_generated.address_a[1]
address_a[2] => altsyncram_fbg1:auto_generated.address_a[2]
address_a[3] => altsyncram_fbg1:auto_generated.address_a[3]
address_a[4] => altsyncram_fbg1:auto_generated.address_a[4]
address_a[5] => altsyncram_fbg1:auto_generated.address_a[5]
address_a[6] => altsyncram_fbg1:auto_generated.address_a[6]
address_a[7] => altsyncram_fbg1:auto_generated.address_a[7]
address_a[8] => altsyncram_fbg1:auto_generated.address_a[8]
address_a[9] => altsyncram_fbg1:auto_generated.address_a[9]
address_a[10] => altsyncram_fbg1:auto_generated.address_a[10]
address_b[0] => altsyncram_fbg1:auto_generated.address_b[0]
address_b[1] => altsyncram_fbg1:auto_generated.address_b[1]
address_b[2] => altsyncram_fbg1:auto_generated.address_b[2]
address_b[3] => altsyncram_fbg1:auto_generated.address_b[3]
address_b[4] => altsyncram_fbg1:auto_generated.address_b[4]
address_b[5] => altsyncram_fbg1:auto_generated.address_b[5]
address_b[6] => altsyncram_fbg1:auto_generated.address_b[6]
address_b[7] => altsyncram_fbg1:auto_generated.address_b[7]
address_b[8] => altsyncram_fbg1:auto_generated.address_b[8]
address_b[9] => altsyncram_fbg1:auto_generated.address_b[9]
address_b[10] => altsyncram_fbg1:auto_generated.address_b[10]
addressstall_a => ~NO_FANOUT~
addressstall_b => ~NO_FANOUT~
clock0 => altsyncram_fbg1:auto_generated.clock0
clock1 => altsyncram_fbg1:auto_generated.clock1
clocken0 => ~NO_FANOUT~
clocken1 => ~NO_FANOUT~
clocken2 => ~NO_FANOUT~
clocken3 => ~NO_FANOUT~
aclr0 => ~NO_FANOUT~
aclr1 => ~NO_FANOUT~
byteena_a[0] => ~NO_FANOUT~
byteena_b[0] => ~NO_FANOUT~
q_a[0] <= <GND>
q_a[1] <= <GND>
q_a[2] <= <GND>
q_a[3] <= <GND>
q_a[4] <= <GND>
q_a[5] <= <GND>
q_a[6] <= <GND>
q_a[7] <= <GND>
q_b[0] <= altsyncram_fbg1:auto_generated.q_b[0]
q_b[1] <= altsyncram_fbg1:auto_generated.q_b[1]
q_b[2] <= altsyncram_fbg1:auto_generated.q_b[2]
q_b[3] <= altsyncram_fbg1:auto_generated.q_b[3]
q_b[4] <= altsyncram_fbg1:auto_generated.q_b[4]
q_b[5] <= altsyncram_fbg1:auto_generated.q_b[5]
q_b[6] <= altsyncram_fbg1:auto_generated.q_b[6]
q_b[7] <= altsyncram_fbg1:auto_generated.q_b[7]
eccstatus[0] <= <GND>
eccstatus[1] <= <GND>
eccstatus[2] <= <GND>


|SCANWAVE|dram:inst14|altsyncram:altsyncram_component|altsyncram_fbg1:auto_generated
address_a[0] => ram_block1a0.PORTAADDR
address_a[0] => ram_block1a1.PORTAADDR
address_a[0] => ram_block1a2.PORTAADDR
address_a[0] => ram_block1a3.PORTAADDR
address_a[0] => ram_block1a4.PORTAADDR
address_a[0] => ram_block1a5.PORTAADDR
address_a[0] => ram_block1a6.PORTAADDR
address_a[0] => ram_block1a7.PORTAADDR
address_a[1] => ram_block1a0.PORTAADDR1
address_a[1] => ram_block1a1.PORTAADDR1
address_a[1] => ram_block1a2.PORTAADDR1
address_a[1] => ram_block1a3.PORTAADDR1
address_a[1] => ram_block1a4.PORTAADDR1
address_a[1] => ram_block1a5.PORTAADDR1
address_a[1] => ram_block1a6.PORTAADDR1
address_a[1] => ram_block1a7.PORTAADDR1
address_a[2] => ram_block1a0.PORTAADDR2
address_a[2] => ram_block1a1.PORTAADDR2
address_a[2] => ram_block1a2.PORTAADDR2
address_a[2] => ram_block1a3.PORTAADDR2
address_a[2] => ram_block1a4.PORTAADDR2
address_a[2] => ram_block1a5.PORTAADDR2
address_a[2] => ram_block1a6.PORTAADDR2
address_a[2] => ram_block1a7.PORTAADDR2
address_a[3] => ram_block1a0.PORTAADDR3
address_a[3] => ram_block1a1.PORTAADDR3
address_a[3] => ram_block1a2.PORTAADDR3
address_a[3] => ram_block1a3.PORTAADDR3
address_a[3] => ram_block1a4.PORTAADDR3
address_a[3] => ram_block1a5.PORTAADDR3
address_a[3] => ram_block1a6.PORTAADDR3
address_a[3] => ram_block1a7.PORTAADDR3
address_a[4] => ram_block1a0.PORTAADDR4
address_a[4] => ram_block1a1.PORTAADDR4
address_a[4] => ram_block1a2.PORTAADDR4
address_a[4] => ram_block1a3.PORTAADDR4
address_a[4] => ram_block1a4.PORTAADDR4
address_a[4] => ram_block1a5.PORTAADDR4
address_a[4] => ram_block1a6.PORTAADDR4
address_a[4] => ram_block1a7.PORTAADDR4
address_a[5] => ram_block1a0.PORTAADDR5
address_a[5] => ram_block1a1.PORTAADDR5
address_a[5] => ram_block1a2.PORTAADDR5
address_a[5] => ram_block1a3.PORTAADDR5
address_a[5] => ram_block1a4.PORTAADDR5
address_a[5] => ram_block1a5.PORTAADDR5
address_a[5] => ram_block1a6.PORTAADDR5
address_a[5] => ram_block1a7.PORTAADDR5
address_a[6] => ram_block1a0.PORTAADDR6
address_a[6] => ram_block1a1.PORTAADDR6
address_a[6] => ram_block1a2.PORTAADDR6
address_a[6] => ram_block1a3.PORTAADDR6
address_a[6] => ram_block1a4.PORTAADDR6
address_a[6] => ram_block1a5.PORTAADDR6
address_a[6] => ram_block1a6.PORTAADDR6
address_a[6] => ram_block1a7.PORTAADDR6
address_a[7] => ram_block1a0.PORTAADDR7
address_a[7] => ram_block1a1.PORTAADDR7
address_a[7] => ram_block1a2.PORTAADDR7
address_a[7] => ram_block1a3.PORTAADDR7
address_a[7] => ram_block1a4.PORTAADDR7
address_a[7] => ram_block1a5.PORTAADDR7
address_a[7] => ram_block1a6.PORTAADDR7
address_a[7] => ram_block1a7.PORTAADDR7
address_a[8] => ram_block1a0.PORTAADDR8
address_a[8] => ram_block1a1.PORTAADDR8
address_a[8] => ram_block1a2.PORTAADDR8
address_a[8] => ram_block1a3.PORTAADDR8
address_a[8] => ram_block1a4.PORTAADDR8
address_a[8] => ram_block1a5.PORTAADDR8
address_a[8] => ram_block1a6.PORTAADDR8
address_a[8] => ram_block1a7.PORTAADDR8
address_a[9] => ram_block1a0.PORTAADDR9
address_a[9] => ram_block1a1.PORTAADDR9
address_a[9] => ram_block1a2.PORTAADDR9
address_a[9] => ram_block1a3.PORTAADDR9
address_a[9] => ram_block1a4.PORTAADDR9
address_a[9] => ram_block1a5.PORTAADDR9
address_a[9] => ram_block1a6.PORTAADDR9
address_a[9] => ram_block1a7.PORTAADDR9
address_a[10] => ram_block1a0.PORTAADDR10
address_a[10] => ram_block1a1.PORTAADDR10
address_a[10] => ram_block1a2.PORTAADDR10
address_a[10] => ram_block1a3.PORTAADDR10
address_a[10] => ram_block1a4.PORTAADDR10
address_a[10] => ram_block1a5.PORTAADDR10
address_a[10] => ram_block1a6.PORTAADDR10
address_a[10] => ram_block1a7.PORTAADDR10
address_b[0] => ram_block1a0.PORTBADDR
address_b[0] => ram_block1a1.PORTBADDR
address_b[0] => ram_block1a2.PORTBADDR
address_b[0] => ram_block1a3.PORTBADDR
address_b[0] => ram_block1a4.PORTBADDR
address_b[0] => ram_block1a5.PORTBADDR
address_b[0] => ram_block1a6.PORTBADDR
address_b[0] => ram_block1a7.PORTBADDR
address_b[1] => ram_block1a0.PORTBADDR1
address_b[1] => ram_block1a1.PORTBADDR1
address_b[1] => ram_block1a2.PORTBADDR1
address_b[1] => ram_block1a3.PORTBADDR1
address_b[1] => ram_block1a4.PORTBADDR1
address_b[1] => ram_block1a5.PORTBADDR1
address_b[1] => ram_block1a6.PORTBADDR1
address_b[1] => ram_block1a7.PORTBADDR1
address_b[2] => ram_block1a0.PORTBADDR2
address_b[2] => ram_block1a1.PORTBADDR2
address_b[2] => ram_block1a2.PORTBADDR2
address_b[2] => ram_block1a3.PORTBADDR2
address_b[2] => ram_block1a4.PORTBADDR2
address_b[2] => ram_block1a5.PORTBADDR2
address_b[2] => ram_block1a6.PORTBADDR2
address_b[2] => ram_block1a7.PORTBADDR2
address_b[3] => ram_block1a0.PORTBADDR3
address_b[3] => ram_block1a1.PORTBADDR3
address_b[3] => ram_block1a2.PORTBADDR3
address_b[3] => ram_block1a3.PORTBADDR3
address_b[3] => ram_block1a4.PORTBADDR3
address_b[3] => ram_block1a5.PORTBADDR3
address_b[3] => ram_block1a6.PORTBADDR3
address_b[3] => ram_block1a7.PORTBADDR3
address_b[4] => ram_block1a0.PORTBADDR4
address_b[4] => ram_block1a1.PORTBADDR4
address_b[4] => ram_block1a2.PORTBADDR4
address_b[4] => ram_block1a3.PORTBADDR4
address_b[4] => ram_block1a4.PORTBADDR4
address_b[4] => ram_block1a5.PORTBADDR4
address_b[4] => ram_block1a6.PORTBADDR4
address_b[4] => ram_block1a7.PORTBADDR4
address_b[5] => ram_block1a0.PORTBADDR5
address_b[5] => ram_block1a1.PORTBADDR5
address_b[5] => ram_block1a2.PORTBADDR5
address_b[5] => ram_block1a3.PORTBADDR5
address_b[5] => ram_block1a4.PORTBADDR5
address_b[5] => ram_block1a5.PORTBADDR5
address_b[5] => ram_block1a6.PORTBADDR5
address_b[5] => ram_block1a7.PORTBADDR5
address_b[6] => ram_block1a0.PORTBADDR6
address_b[6] => ram_block1a1.PORTBADDR6
address_b[6] => ram_block1a2.PORTBADDR6
address_b[6] => ram_block1a3.PORTBADDR6
address_b[6] => ram_block1a4.PORTBADDR6
address_b[6] => ram_block1a5.PORTBADDR6
address_b[6] => ram_block1a6.PORTBADDR6
address_b[6] => ram_block1a7.PORTBADDR6
address_b[7] => ram_block1a0.PORTBADDR7
address_b[7] => ram_block1a1.PORTBADDR7
address_b[7] => ram_block1a2.PORTBADDR7
address_b[7] => ram_block1a3.PORTBADDR7
address_b[7] => ram_block1a4.PORTBADDR7
address_b[7] => ram_block1a5.PORTBADDR7
address_b[7] => ram_block1a6.PORTBADDR7
address_b[7] => ram_block1a7.PORTBADDR7
address_b[8] => ram_block1a0.PORTBADDR8
address_b[8] => ram_block1a1.PORTBADDR8
address_b[8] => ram_block1a2.PORTBADDR8
address_b[8] => ram_block1a3.PORTBADDR8
address_b[8] => ram_block1a4.PORTBADDR8
address_b[8] => ram_block1a5.PORTBADDR8
address_b[8] => ram_block1a6.PORTBADDR8
address_b[8] => ram_block1a7.PORTBADDR8
address_b[9] => ram_block1a0.PORTBADDR9
address_b[9] => ram_block1a1.PORTBADDR9
address_b[9] => ram_block1a2.PORTBADDR9
address_b[9] => ram_block1a3.PORTBADDR9
address_b[9] => ram_block1a4.PORTBADDR9
address_b[9] => ram_block1a5.PORTBADDR9
address_b[9] => ram_block1a6.PORTBADDR9
address_b[9] => ram_block1a7.PORTBADDR9
address_b[10] => ram_block1a0.PORTBADDR10
address_b[10] => ram_block1a1.PORTBADDR10
address_b[10] => ram_block1a2.PORTBADDR10
address_b[10] => ram_block1a3.PORTBADDR10
address_b[10] => ram_block1a4.PORTBADDR10
address_b[10] => ram_block1a5.PORTBADDR10
address_b[10] => ram_block1a6.PORTBADDR10
address_b[10] => ram_block1a7.PORTBADDR10
clock0 => ram_block1a0.CLK0
clock0 => ram_block1a1.CLK0
clock0 => ram_block1a2.CLK0
clock0 => ram_block1a3.CLK0
clock0 => ram_block1a4.CLK0
clock0 => ram_block1a5.CLK0
clock0 => ram_block1a6.CLK0
clock0 => ram_block1a7.CLK0
clock1 => ram_block1a0.CLK1
clock1 => ram_block1a1.CLK1
clock1 => ram_block1a2.CLK1
clock1 => ram_block1a3.CLK1
clock1 => ram_block1a4.CLK1
clock1 => ram_block1a5.CLK1
clock1 => ram_block1a6.CLK1
clock1 => ram_block1a7.CLK1
data_a[0] => ram_block1a0.PORTADATAIN
data_a[1] => ram_block1a1.PORTADATAIN
data_a[2] => ram_block1a2.PORTADATAIN
data_a[3] => ram_block1a3.PORTADATAIN
data_a[4] => ram_block1a4.PORTADATAIN
data_a[5] => ram_block1a5.PORTADATAIN
data_a[6] => ram_block1a6.PORTADATAIN
data_a[7] => ram_block1a7.PORTADATAIN
q_b[0] <= ram_block1a0.PORTBDATAOUT
q_b[1] <= ram_block1a1.PORTBDATAOUT
q_b[2] <= ram_block1a2.PORTBDATAOUT
q_b[3] <= ram_block1a3.PORTBDATAOUT
q_b[4] <= ram_block1a4.PORTBDATAOUT
q_b[5] <= ram_block1a5.PORTBDATAOUT
q_b[6] <= ram_block1a6.PORTBDATAOUT
q_b[7] <= ram_block1a7.PORTBDATAOUT
wren_a => ram_block1a0.ENA0
wren_a => ram_block1a1.ENA0
wren_a => ram_block1a2.ENA0
wren_a => ram_block1a3.ENA0
wren_a => ram_block1a4.ENA0
wren_a => ram_block1a5.ENA0
wren_a => ram_block1a6.ENA0
wren_a => ram_block1a7.ENA0


|SCANWAVE|VOLTAGE_CONV:inst9
ADEN => TEMP[7].ACLR
ADEN => TEMP[6].ACLR
ADEN => TEMP[5].ACLR
ADEN => TEMP[4].ACLR
ADEN => TEMP[3].ACLR
ADEN => TEMP[2].ACLR
ADEN => TEMP[1].ACLR
ADEN => TEMP[0].ACLR
CLKK => TEMP[7].CLK
CLKK => TEMP[6].CLK
CLKK => TEMP[5].CLK
CLKK => TEMP[4].CLK
CLKK => TEMP[3].CLK
CLKK => TEMP[2].CLK
CLKK => TEMP[1].CLK
CLKK => TEMP[0].CLK
DATA[0] => Add0.IN8
DATA[0] => LessThan0.IN16
DATA[1] => Add0.IN7
DATA[1] => LessThan0.IN15
DATA[2] => Add0.IN6
DATA[2] => LessThan0.IN14
DATA[3] => Add0.IN5
DATA[3] => LessThan0.IN13
DATA[4] => Add0.IN4
DATA[4] => LessThan0.IN12
DATA[5] => Add0.IN3
DATA[5] => LessThan0.IN11
DATA[6] => Add0.IN2
DATA[6] => LessThan0.IN10
DATA[7] => Add0.IN1
DATA[7] => LessThan0.IN9
POSY_A[0] => Add0.IN16
POSY_A[1] => Add0.IN15
POSY_A[2] => Add0.IN14
POSY_A[3] => Add0.IN13
POSY_A[4] => Add0.IN12
POSY_A[5] => Add0.IN11
POSY_A[6] => Add0.IN10
POSY_A[7] => Add0.IN9
Q[0] <= TEMP[0].DB_MAX_OUTPUT_PORT_TYPE
Q[1] <= TEMP[1].DB_MAX_OUTPUT_PORT_TYPE
Q[2] <= TEMP[2].DB_MAX_OUTPUT_PORT_TYPE
Q[3] <= TEMP[3].DB_MAX_OUTPUT_PORT_TYPE
Q[4] <= TEMP[4].DB_MAX_OUTPUT_PORT_TYPE
Q[5] <= TEMP[5].DB_MAX_OUTPUT_PORT_TYPE
Q[6] <= TEMP[6].DB_MAX_OUTPUT_PORT_TYPE
Q[7] <= TEMP[7].DB_MAX_OUTPUT_PORT_TYPE


|SCANWAVE|MUX2_1:inst32
X1[0] => Q~7.DATAB
X1[1] => Q~6.DATAB
X1[2] => Q~5.DATAB
X1[3] => Q~4.DATAB
X1[4] => Q~3.DATAB
X1[5] => Q~2.DATAB
X1[6] => Q~1.DATAB
X1[7] => Q~0.DATAB
X2[0] => Q~7.DATAA
X2[1] => Q~6.DATAA
X2[2] => Q~5.DATAA
X2[3] => Q~4.DATAA
X2[4] => Q~3.DATAA
X2[5] => Q~2.DATAA
X2[6] => Q~1.DATAA
X2[7] => Q~0.DATAA
SEL => Q~7.OUTPUTSELECT
SEL => Q~6.OUTPUTSELECT
SEL => Q~5.OUTPUTSELECT
SEL => Q~4.OUTPUTSELECT
SEL => Q~3.OUTPUTSELECT
SEL => Q~2.OUTPUTSELECT
SEL => Q~1.OUTPUTSELECT
SEL => Q~0.OUTPUTSELECT
Q[0] <= Q~7.DB_MAX_OUTPUT_PORT_TYPE
Q[1] <= Q~6.DB_MAX_OUTPUT_PORT_TYPE
Q[2] <= Q~5.DB_MAX_OUTPUT_PORT_TYPE
Q[3] <= Q~4.DB_MAX_OUTPUT_PORT_TYPE
Q[4] <= Q~3.DB_MAX_OUTPUT_PORT_TYPE
Q[5] <= Q~2.DB_MAX_OUTPUT_PORT_TYPE
Q[6] <= Q~1.DB_MAX_OUTPUT_PORT_TYPE
Q[7] <= Q~0.DB_MAX_OUTPUT_PORT_TYPE