scanwave.hier_info

数字示波器的FPGA实现 VHDL编写 Quartus7.1测试通过

tridata[3] <= dout[3]
tridata[4] <= dout[4]
tridata[5] <= dout[5]
tridata[6] <= dout[6]
tridata[7] <= dout[7]
data[0] => dout[0].DATAIN
data[1] => dout[1].DATAIN
data[2] => dout[2].DATAIN
data[3] => dout[3].DATAIN
data[4] => dout[4].DATAIN
data[5] => dout[5].DATAIN
data[6] => dout[6].DATAIN
data[7] => dout[7].DATAIN
enabletr => din[7].OE
enabletr => din[6].OE
enabletr => din[5].OE
enabletr => din[4].OE
enabletr => din[3].OE
enabletr => din[2].OE
enabletr => din[1].OE
enabletr => din[0].OE
enabledt => dout[7].OE
enabledt => dout[6].OE
enabledt => dout[5].OE
enabledt => dout[4].OE
enabledt => dout[3].OE
enabledt => dout[2].OE
enabledt => dout[1].OE
enabledt => dout[0].OE
result[0] <= din[0].DB_MAX_OUTPUT_PORT_TYPE
result[1] <= din[1].DB_MAX_OUTPUT_PORT_TYPE
result[2] <= din[2].DB_MAX_OUTPUT_PORT_TYPE
result[3] <= din[3].DB_MAX_OUTPUT_PORT_TYPE
result[4] <= din[4].DB_MAX_OUTPUT_PORT_TYPE
result[5] <= din[5].DB_MAX_OUTPUT_PORT_TYPE
result[6] <= din[6].DB_MAX_OUTPUT_PORT_TYPE
result[7] <= din[7].DB_MAX_OUTPUT_PORT_TYPE


|SCANWAVE|FREQ_COUNT:inst6
CLK => COUNT1[15].CLK
CLK => COUNT1[14].CLK
CLK => COUNT1[13].CLK
CLK => COUNT1[12].CLK
CLK => COUNT1[11].CLK
CLK => COUNT1[10].CLK
CLK => COUNT1[9].CLK
CLK => COUNT1[8].CLK
CLK => COUNT1[7].CLK
CLK => COUNT1[6].CLK
CLK => COUNT1[5].CLK
CLK => COUNT1[4].CLK
CLK => COUNT1[3].CLK
CLK => COUNT1[2].CLK
CLK => COUNT1[1].CLK
CLK => COUNT1[0].CLK
CLK => FULL.CLK
CLK2 => COUNT2[16].CLK
CLK2 => COUNT2[15].CLK
CLK2 => COUNT2[14].CLK
CLK2 => COUNT2[13].CLK
CLK2 => COUNT2[12].CLK
CLK2 => COUNT2[11].CLK
CLK2 => COUNT2[10].CLK
CLK2 => COUNT2[9].CLK
CLK2 => COUNT2[8].CLK
CLK2 => COUNT2[7].CLK
CLK2 => COUNT2[6].CLK
CLK2 => COUNT2[5].CLK
CLK2 => COUNT2[4].CLK
CLK2 => COUNT2[3].CLK
CLK2 => COUNT2[2].CLK
CLK2 => COUNT2[1].CLK
CLK2 => COUNT2[0].CLK
CLK2 => TEMP[15].CLK
CLK2 => TEMP[14].CLK
CLK2 => TEMP[13].CLK
CLK2 => TEMP[12].CLK
CLK2 => TEMP[11].CLK
CLK2 => TEMP[10].CLK
CLK2 => TEMP[9].CLK
CLK2 => TEMP[8].CLK
CLK2 => TEMP[7].CLK
CLK2 => TEMP[6].CLK
CLK2 => TEMP[5].CLK
CLK2 => TEMP[4].CLK
CLK2 => TEMP[3].CLK
CLK2 => TEMP[2].CLK
CLK2 => TEMP[1].CLK
CLK2 => TEMP[0].CLK
CLR => COUNT1[15].ACLR
CLR => COUNT1[14].ACLR
CLR => COUNT1[13].ACLR
CLR => COUNT1[12].ACLR
CLR => COUNT1[11].ACLR
CLR => COUNT1[10].ACLR
CLR => COUNT1[9].ACLR
CLR => COUNT1[8].ACLR
CLR => COUNT1[7].ACLR
CLR => COUNT1[6].ACLR
CLR => COUNT1[5].ACLR
CLR => COUNT1[4].ACLR
CLR => COUNT1[3].ACLR
CLR => COUNT1[2].ACLR
CLR => COUNT1[1].ACLR
CLR => COUNT1[0].ACLR
CLR => FULL.ACLR
CLR => COUNT2[16].ACLR
CLR => COUNT2[15].ACLR
CLR => COUNT2[14].ACLR
CLR => COUNT2[13].ACLR
CLR => COUNT2[12].ACLR
CLR => COUNT2[11].ACLR
CLR => COUNT2[10].ACLR
CLR => COUNT2[9].ACLR
CLR => COUNT2[8].ACLR
CLR => COUNT2[7].ACLR
CLR => COUNT2[6].ACLR
CLR => COUNT2[5].ACLR
CLR => COUNT2[4].ACLR
CLR => COUNT2[3].ACLR
CLR => COUNT2[2].ACLR
CLR => COUNT2[1].ACLR
CLR => COUNT2[0].ACLR
CLR => TEMP[15].ENA
CLR => TEMP[14].ENA
CLR => TEMP[13].ENA
CLR => TEMP[12].ENA
CLR => TEMP[11].ENA
CLR => TEMP[10].ENA
CLR => TEMP[9].ENA
CLR => TEMP[8].ENA
CLR => TEMP[7].ENA
CLR => TEMP[6].ENA
CLR => TEMP[5].ENA
CLR => TEMP[4].ENA
CLR => TEMP[3].ENA
CLR => TEMP[2].ENA
CLR => TEMP[1].ENA
CLR => TEMP[0].ENA
QH[0] <= TEMP[8].DB_MAX_OUTPUT_PORT_TYPE
QH[1] <= TEMP[9].DB_MAX_OUTPUT_PORT_TYPE
QH[2] <= TEMP[10].DB_MAX_OUTPUT_PORT_TYPE
QH[3] <= TEMP[11].DB_MAX_OUTPUT_PORT_TYPE
QH[4] <= TEMP[12].DB_MAX_OUTPUT_PORT_TYPE
QH[5] <= TEMP[13].DB_MAX_OUTPUT_PORT_TYPE
QH[6] <= TEMP[14].DB_MAX_OUTPUT_PORT_TYPE
QH[7] <= TEMP[15].DB_MAX_OUTPUT_PORT_TYPE
QL[0] <= TEMP[0].DB_MAX_OUTPUT_PORT_TYPE
QL[1] <= TEMP[1].DB_MAX_OUTPUT_PORT_TYPE
QL[2] <= TEMP[2].DB_MAX_OUTPUT_PORT_TYPE
QL[3] <= TEMP[3].DB_MAX_OUTPUT_PORT_TYPE
QL[4] <= TEMP[4].DB_MAX_OUTPUT_PORT_TYPE
QL[5] <= TEMP[5].DB_MAX_OUTPUT_PORT_TYPE
QL[6] <= TEMP[6].DB_MAX_OUTPUT_PORT_TYPE
QL[7] <= TEMP[7].DB_MAX_OUTPUT_PORT_TYPE


|SCANWAVE|FREDEVIDER10:inst18
CLKIN => COUNTER[6].CLK
CLKIN => COUNTER[5].CLK
CLKIN => COUNTER[4].CLK
CLKIN => COUNTER[3].CLK
CLKIN => COUNTER[2].CLK
CLKIN => COUNTER[1].CLK
CLKIN => COUNTER[0].CLK
CLKIN => CLK.CLK
CLKOUT <= CLK.DB_MAX_OUTPUT_PORT_TYPE


|SCANWAVE|MUX2_3:inst3
X1[0] => Mux7.IN1
X1[1] => Mux6.IN1
X1[2] => Mux5.IN1
X1[3] => Mux4.IN1
X1[4] => Mux3.IN1
X1[5] => Mux2.IN1
X1[6] => Mux1.IN1
X1[7] => Mux0.IN1
X2[0] => Mux7.IN2
X2[1] => Mux6.IN2
X2[2] => Mux5.IN2
X2[3] => Mux4.IN2
X2[4] => Mux3.IN2
X2[5] => Mux2.IN2
X2[6] => Mux1.IN2
X2[7] => Mux0.IN2
X3[0] => Mux7.IN3
X3[1] => Mux6.IN3
X3[2] => Mux5.IN3
X3[3] => Mux4.IN3
X3[4] => Mux3.IN3
X3[5] => Mux2.IN3
X3[6] => Mux1.IN3
X3[7] => Mux0.IN3
SEL_AB[0] => Mux7.IN5
SEL_AB[0] => Mux6.IN5
SEL_AB[0] => Mux5.IN5
SEL_AB[0] => Mux4.IN5
SEL_AB[0] => Mux3.IN5
SEL_AB[0] => Mux2.IN5
SEL_AB[0] => Mux1.IN5
SEL_AB[0] => Mux0.IN5
SEL_AB[1] => Mux7.IN4
SEL_AB[1] => Mux6.IN4
SEL_AB[1] => Mux5.IN4
SEL_AB[1] => Mux4.IN4
SEL_AB[1] => Mux3.IN4
SEL_AB[1] => Mux2.IN4
SEL_AB[1] => Mux1.IN4
SEL_AB[1] => Mux0.IN4
Q[0] <= Mux7.DB_MAX_OUTPUT_PORT_TYPE
Q[1] <= Mux6.DB_MAX_OUTPUT_PORT_TYPE
Q[2] <= Mux5.DB_MAX_OUTPUT_PORT_TYPE
Q[3] <= Mux4.DB_MAX_OUTPUT_PORT_TYPE
Q[4] <= Mux3.DB_MAX_OUTPUT_PORT_TYPE
Q[5] <= Mux2.DB_MAX_OUTPUT_PORT_TYPE
Q[6] <= Mux1.DB_MAX_OUTPUT_PORT_TYPE
Q[7] <= Mux0.DB_MAX_OUTPUT_PORT_TYPE


|SCANWAVE|VOLTAGE_CONV:inst17
ADEN => TEMP[7].ACLR
ADEN => TEMP[6].ACLR
ADEN => TEMP[5].ACLR
ADEN => TEMP[4].ACLR
ADEN => TEMP[3].ACLR
ADEN => TEMP[2].ACLR
ADEN => TEMP[1].ACLR
ADEN => TEMP[0].ACLR
CLKK => TEMP[7].CLK
CLKK => TEMP[6].CLK
CLKK => TEMP[5].CLK
CLKK => TEMP[4].CLK
CLKK => TEMP[3].CLK
CLKK => TEMP[2].CLK
CLKK => TEMP[1].CLK
CLKK => TEMP[0].CLK
DATA[0] => Add0.IN8
DATA[0] => LessThan0.IN16
DATA[1] => Add0.IN7
DATA[1] => LessThan0.IN15
DATA[2] => Add0.IN6
DATA[2] => LessThan0.IN14
DATA[3] => Add0.IN5
DATA[3] => LessThan0.IN13
DATA[4] => Add0.IN4
DATA[4] => LessThan0.IN12
DATA[5] => Add0.IN3
DATA[5] => LessThan0.IN11
DATA[6] => Add0.IN2
DATA[6] => LessThan0.IN10
DATA[7] => Add0.IN1
DATA[7] => LessThan0.IN9
POSY_A[0] => Add0.IN16
POSY_A[1] => Add0.IN15
POSY_A[2] => Add0.IN14
POSY_A[3] => Add0.IN13
POSY_A[4] => Add0.IN12
POSY_A[5] => Add0.IN11
POSY_A[6] => Add0.IN10
POSY_A[7] => Add0.IN9
Q[0] <= TEMP[0].DB_MAX_OUTPUT_PORT_TYPE
Q[1] <= TEMP[1].DB_MAX_OUTPUT_PORT_TYPE
Q[2] <= TEMP[2].DB_MAX_OUTPUT_PORT_TYPE
Q[3] <= TEMP[3].DB_MAX_OUTPUT_PORT_TYPE
Q[4] <= TEMP[4].DB_MAX_OUTPUT_PORT_TYPE
Q[5] <= TEMP[5].DB_MAX_OUTPUT_PORT_TYPE
Q[6] <= TEMP[6].DB_MAX_OUTPUT_PORT_TYPE
Q[7] <= TEMP[7].DB_MAX_OUTPUT_PORT_TYPE


|SCANWAVE|AD_SRAM:inst20
CLK => cnt2[11].CLK
CLK => cnt2[10].CLK
CLK => cnt2[9].CLK
CLK => cnt2[8].CLK
CLK => cnt2[7].CLK
CLK => cnt2[6].CLK
CLK => cnt2[5].CLK
CLK => cnt2[4].CLK
CLK => cnt2[3].CLK
CLK => cnt2[2].CLK
CLK => cnt2[1].CLK
CLK => cnt2[0].CLK
CLK => cnt[2].CLK
CLK => cnt[1].CLK
CLK => cnt[0].CLK
CLK => data[7].CLK
CLK => data[6].CLK
CLK => data[5].CLK
CLK => data[4].CLK
CLK => data[3].CLK
CLK => data[2].CLK
CLK => data[1].CLK
CLK => data[0].CLK
EN => ADEN.DATAIN
EN => cnt2[11].ACLR
EN => cnt2[10].ACLR
EN => cnt2[9].ACLR
EN => cnt2[8].ACLR
EN => cnt2[7].ACLR
EN => cnt2[6].ACLR
EN => cnt2[5].ACLR
EN => cnt2[4].ACLR
EN => cnt2[3].ACLR
EN => cnt2[2].ACLR
EN => cnt2[1].ACLR
EN => cnt2[0].ACLR
EN => cnt[2].ACLR
EN => cnt[1].ACLR
EN => cnt[0].ACLR
EN => data[0].ENA
EN => data[7].ENA
EN => data[6].ENA
EN => data[5].ENA
EN => data[4].ENA
EN => data[3].ENA
EN => data[2].ENA
EN => data[1].ENA
SAVE => cnt~2.OUTPUTSELECT
SAVE => cnt~1.OUTPUTSELECT
SAVE => cnt~0.OUTPUTSELECT
lock => cnt2~11.OUTPUTSELECT
lock => cnt2~10.OUTPUTSELECT
lock => cnt2~9.OUTPUTSELECT
lock => cnt2~8.OUTPUTSELECT
lock => cnt2~7.OUTPUTSELECT
lock => cnt2~6.OUTPUTSELECT
lock => cnt2~5.OUTPUTSELECT
lock => cnt2~4.OUTPUTSELECT
lock => cnt2~3.OUTPUTSELECT
lock => cnt2~2.OUTPUTSELECT
lock => cnt2~1.OUTPUTSELECT
lock => cnt2~0.OUTPUTSELECT
lock => cnt~5.OUTPUTSELECT
lock => cnt~4.OUTPUTSELECT
lock => cnt~3.OUTPUTSELECT
AIN[0] => Mux10.IN0
AIN[1] => Mux9.IN0
AIN[2] => Mux8.IN0
AIN[3] => Mux7.IN0
AIN[4] => Mux6.IN0
AIN[5] => Mux5.IN0
AIN[6] => Mux4.IN0
AIN[7] => Mux3.IN0
ADEN <= EN.DB_MAX_OUTPUT_PORT_TYPE
DATASOUT[0] <= data[0].DB_MAX_OUTPUT_PORT_TYPE
DATASOUT[1] <= data[1].DB_MAX_OUTPUT_PORT_TYPE
DATASOUT[2] <= data[2].DB_MAX_OUTPUT_PORT_TYPE
DATASOUT[3] <= data[3].DB_MAX_OUTPUT_PORT_TYPE
DATASOUT[4] <= data[4].DB_MAX_OUTPUT_PORT_TYPE
DATASOUT[5] <= data[5].DB_MAX_OUTPUT_PORT_TYPE
DATASOUT[6] <= data[6].DB_MAX_OUTPUT_PORT_TYPE
DATASOUT[7] <= data[7].DB_MAX_OUTPUT_PORT_TYPE
ADDOUT[0] <= cnt2[0].DB_MAX_OUTPUT_PORT_TYPE
ADDOUT[1] <= cnt2[1].DB_MAX_OUTPUT_PORT_TYPE
ADDOUT[2] <= cnt2[2].DB_MAX_OUTPUT_PORT_TYPE
ADDOUT[3] <= cnt2[3].DB_MAX_OUTPUT_PORT_TYPE
ADDOUT[4] <= cnt2[4].DB_MAX_OUTPUT_PORT_TYPE
ADDOUT[5] <= cnt2[5].DB_MAX_OUTPUT_PORT_TYPE
ADDOUT[6] <= cnt2[6].DB_MAX_OUTPUT_PORT_TYPE
ADDOUT[7] <= cnt2[7].DB_MAX_OUTPUT_PORT_TYPE
ADDOUT[8] <= cnt2[8].DB_MAX_OUTPUT_PORT_TYPE
ADDOUT[9] <= cnt2[9].DB_MAX_OUTPUT_PORT_TYPE
ADDOUT[10] <= cnt2[10].DB_MAX_OUTPUT_PORT_TYPE
WRS1 <= <VCC>


|SCANWAVE|dram:inst14
data[0] => altsyncram:altsyncram_component.data_a[0]
data[1] => altsyncram:altsyncram_component.data_a[1]
data[2] => altsyncram:altsyncram_component.data_a[2]
data[3] => altsyncram:altsyncram_component.data_a[3]
data[4] => altsyncram:altsyncram_component.data_a[4]
data[5] => altsyncram:altsyncram_component.data_a[5]
data[6] => altsyncram:altsyncram_component.data_a[6]
data[7] => altsyncram:altsyncram_component.data_a[7]
wren => altsyncram:altsyncram_component.wren_a
wraddress[0] => altsyncram:altsyncram_component.address_a[0]
wraddress[1] => altsyncram:altsyncram_component.address_a[1]
wraddress[2] => altsyncram:altsyncram_component.address_a[2]
wraddress[3] => altsyncram:altsyncram_component.address_a[3]
wraddress[4] => altsyncram:altsyncram_component.address_a[4]
wraddress[5] => altsyncram:altsyncram_component.address_a[5]
wraddress[6] => altsyncram:altsyncram_component.address_a[6]
wraddress[7] => altsyncram:altsyncram_component.address_a[7]
wraddress[8] => altsyncram:altsyncram_component.address_a[8]
wraddress[9] => altsyncram:altsyncram_component.address_a[9]
wraddress[10] => altsyncram:altsyncram_component.address_a[10]
rdaddress[0] => altsyncram:altsyncram_component.address_b[0]
rdaddress[1] => altsyncram:altsyncram_component.address_b[1]
rdaddress[2] => altsyncram:altsyncram_component.address_b[2]
rdaddress[3] => altsyncram:altsyncram_component.address_b[3]
rdaddress[4] => altsyncram:altsyncram_component.address_b[4]
rdaddress[5] => altsyncram:altsyncram_component.address_b[5]
rdaddress[6] => altsyncram:altsyncram_component.address_b[6]
rdaddress[7] => altsyncram:altsyncram_component.address_b[7]