scanwave.hier_info

数字示波器的FPGA实现 VHDL编写 Quartus7.1测试通过

address_b[6] => ram_block1a6.PORTBADDR6
address_b[6] => ram_block1a7.PORTBADDR6
address_b[7] => ram_block1a0.PORTBADDR7
address_b[7] => ram_block1a1.PORTBADDR7
address_b[7] => ram_block1a2.PORTBADDR7
address_b[7] => ram_block1a3.PORTBADDR7
address_b[7] => ram_block1a4.PORTBADDR7
address_b[7] => ram_block1a5.PORTBADDR7
address_b[7] => ram_block1a6.PORTBADDR7
address_b[7] => ram_block1a7.PORTBADDR7
address_b[8] => ram_block1a0.PORTBADDR8
address_b[8] => ram_block1a1.PORTBADDR8
address_b[8] => ram_block1a2.PORTBADDR8
address_b[8] => ram_block1a3.PORTBADDR8
address_b[8] => ram_block1a4.PORTBADDR8
address_b[8] => ram_block1a5.PORTBADDR8
address_b[8] => ram_block1a6.PORTBADDR8
address_b[8] => ram_block1a7.PORTBADDR8
address_b[9] => ram_block1a0.PORTBADDR9
address_b[9] => ram_block1a1.PORTBADDR9
address_b[9] => ram_block1a2.PORTBADDR9
address_b[9] => ram_block1a3.PORTBADDR9
address_b[9] => ram_block1a4.PORTBADDR9
address_b[9] => ram_block1a5.PORTBADDR9
address_b[9] => ram_block1a6.PORTBADDR9
address_b[9] => ram_block1a7.PORTBADDR9
address_b[10] => ram_block1a0.PORTBADDR10
address_b[10] => ram_block1a1.PORTBADDR10
address_b[10] => ram_block1a2.PORTBADDR10
address_b[10] => ram_block1a3.PORTBADDR10
address_b[10] => ram_block1a4.PORTBADDR10
address_b[10] => ram_block1a5.PORTBADDR10
address_b[10] => ram_block1a6.PORTBADDR10
address_b[10] => ram_block1a7.PORTBADDR10
clock0 => ram_block1a0.CLK0
clock0 => ram_block1a1.CLK0
clock0 => ram_block1a2.CLK0
clock0 => ram_block1a3.CLK0
clock0 => ram_block1a4.CLK0
clock0 => ram_block1a5.CLK0
clock0 => ram_block1a6.CLK0
clock0 => ram_block1a7.CLK0
clock1 => ram_block1a0.CLK1
clock1 => ram_block1a1.CLK1
clock1 => ram_block1a2.CLK1
clock1 => ram_block1a3.CLK1
clock1 => ram_block1a4.CLK1
clock1 => ram_block1a5.CLK1
clock1 => ram_block1a6.CLK1
clock1 => ram_block1a7.CLK1
data_a[0] => ram_block1a0.PORTADATAIN
data_a[1] => ram_block1a1.PORTADATAIN
data_a[2] => ram_block1a2.PORTADATAIN
data_a[3] => ram_block1a3.PORTADATAIN
data_a[4] => ram_block1a4.PORTADATAIN
data_a[5] => ram_block1a5.PORTADATAIN
data_a[6] => ram_block1a6.PORTADATAIN
data_a[7] => ram_block1a7.PORTADATAIN
q_b[0] <= ram_block1a0.PORTBDATAOUT
q_b[1] <= ram_block1a1.PORTBDATAOUT
q_b[2] <= ram_block1a2.PORTBDATAOUT
q_b[3] <= ram_block1a3.PORTBDATAOUT
q_b[4] <= ram_block1a4.PORTBDATAOUT
q_b[5] <= ram_block1a5.PORTBDATAOUT
q_b[6] <= ram_block1a6.PORTBDATAOUT
q_b[7] <= ram_block1a7.PORTBDATAOUT
wren_a => ram_block1a0.ENA0
wren_a => ram_block1a1.ENA0
wren_a => ram_block1a2.ENA0
wren_a => ram_block1a3.ENA0
wren_a => ram_block1a4.ENA0
wren_a => ram_block1a5.ENA0
wren_a => ram_block1a6.ENA0
wren_a => ram_block1a7.ENA0


|SCANWAVE|AD_SRAM:inst19
CLK => cnt2[11].CLK
CLK => cnt2[10].CLK
CLK => cnt2[9].CLK
CLK => cnt2[8].CLK
CLK => cnt2[7].CLK
CLK => cnt2[6].CLK
CLK => cnt2[5].CLK
CLK => cnt2[4].CLK
CLK => cnt2[3].CLK
CLK => cnt2[2].CLK
CLK => cnt2[1].CLK
CLK => cnt2[0].CLK
CLK => cnt[2].CLK
CLK => cnt[1].CLK
CLK => cnt[0].CLK
CLK => data[7].CLK
CLK => data[6].CLK
CLK => data[5].CLK
CLK => data[4].CLK
CLK => data[3].CLK
CLK => data[2].CLK
CLK => data[1].CLK
CLK => data[0].CLK
EN => ADEN.DATAIN
EN => cnt2[11].ACLR
EN => cnt2[10].ACLR
EN => cnt2[9].ACLR
EN => cnt2[8].ACLR
EN => cnt2[7].ACLR
EN => cnt2[6].ACLR
EN => cnt2[5].ACLR
EN => cnt2[4].ACLR
EN => cnt2[3].ACLR
EN => cnt2[2].ACLR
EN => cnt2[1].ACLR
EN => cnt2[0].ACLR
EN => cnt[2].ACLR
EN => cnt[1].ACLR
EN => cnt[0].ACLR
EN => data[0].ENA
EN => data[7].ENA
EN => data[6].ENA
EN => data[5].ENA
EN => data[4].ENA
EN => data[3].ENA
EN => data[2].ENA
EN => data[1].ENA
SAVE => cnt~2.OUTPUTSELECT
SAVE => cnt~1.OUTPUTSELECT
SAVE => cnt~0.OUTPUTSELECT
lock => cnt2~11.OUTPUTSELECT
lock => cnt2~10.OUTPUTSELECT
lock => cnt2~9.OUTPUTSELECT
lock => cnt2~8.OUTPUTSELECT
lock => cnt2~7.OUTPUTSELECT
lock => cnt2~6.OUTPUTSELECT
lock => cnt2~5.OUTPUTSELECT
lock => cnt2~4.OUTPUTSELECT
lock => cnt2~3.OUTPUTSELECT
lock => cnt2~2.OUTPUTSELECT
lock => cnt2~1.OUTPUTSELECT
lock => cnt2~0.OUTPUTSELECT
lock => cnt~5.OUTPUTSELECT
lock => cnt~4.OUTPUTSELECT
lock => cnt~3.OUTPUTSELECT
AIN[0] => Mux10.IN0
AIN[1] => Mux9.IN0
AIN[2] => Mux8.IN0
AIN[3] => Mux7.IN0
AIN[4] => Mux6.IN0
AIN[5] => Mux5.IN0
AIN[6] => Mux4.IN0
AIN[7] => Mux3.IN0
ADEN <= EN.DB_MAX_OUTPUT_PORT_TYPE
DATASOUT[0] <= data[0].DB_MAX_OUTPUT_PORT_TYPE
DATASOUT[1] <= data[1].DB_MAX_OUTPUT_PORT_TYPE
DATASOUT[2] <= data[2].DB_MAX_OUTPUT_PORT_TYPE
DATASOUT[3] <= data[3].DB_MAX_OUTPUT_PORT_TYPE
DATASOUT[4] <= data[4].DB_MAX_OUTPUT_PORT_TYPE
DATASOUT[5] <= data[5].DB_MAX_OUTPUT_PORT_TYPE
DATASOUT[6] <= data[6].DB_MAX_OUTPUT_PORT_TYPE
DATASOUT[7] <= data[7].DB_MAX_OUTPUT_PORT_TYPE
ADDOUT[0] <= cnt2[0].DB_MAX_OUTPUT_PORT_TYPE
ADDOUT[1] <= cnt2[1].DB_MAX_OUTPUT_PORT_TYPE
ADDOUT[2] <= cnt2[2].DB_MAX_OUTPUT_PORT_TYPE
ADDOUT[3] <= cnt2[3].DB_MAX_OUTPUT_PORT_TYPE
ADDOUT[4] <= cnt2[4].DB_MAX_OUTPUT_PORT_TYPE
ADDOUT[5] <= cnt2[5].DB_MAX_OUTPUT_PORT_TYPE
ADDOUT[6] <= cnt2[6].DB_MAX_OUTPUT_PORT_TYPE
ADDOUT[7] <= cnt2[7].DB_MAX_OUTPUT_PORT_TYPE
ADDOUT[8] <= cnt2[8].DB_MAX_OUTPUT_PORT_TYPE
ADDOUT[9] <= cnt2[9].DB_MAX_OUTPUT_PORT_TYPE
ADDOUT[10] <= cnt2[10].DB_MAX_OUTPUT_PORT_TYPE
WRS1 <= <VCC>


|SCANWAVE|CONV_SINGLE:inst22
CLK => CURRENT_STATE~0.IN1
SINGLE => Selector4.IN3
SINGLE => NEXT_STATE~1.DATAA
SINGLE => Selector1.IN3
SINGLE => Selector0.IN1
SINGLE => NEXT_STATE~0.DATAA
SINGLE => Selector0.IN2
ADDATA[0] => LessThan1.IN8
ADDATA[0] => LessThan0.IN8
ADDATA[0] => Equal0.IN7
ADDATA[1] => LessThan1.IN7
ADDATA[1] => LessThan0.IN7
ADDATA[1] => Equal0.IN6
ADDATA[2] => LessThan1.IN6
ADDATA[2] => LessThan0.IN6
ADDATA[2] => Equal0.IN5
ADDATA[3] => LessThan1.IN5
ADDATA[3] => LessThan0.IN5
ADDATA[3] => Equal0.IN4
ADDATA[4] => LessThan1.IN4
ADDATA[4] => LessThan0.IN4
ADDATA[4] => Equal0.IN3
ADDATA[5] => LessThan1.IN3
ADDATA[5] => LessThan0.IN3
ADDATA[5] => Equal0.IN2
ADDATA[6] => LessThan1.IN2
ADDATA[6] => LessThan0.IN2
ADDATA[6] => Equal0.IN1
ADDATA[7] => LessThan1.IN1
ADDATA[7] => LessThan0.IN1
ADDATA[7] => Equal0.IN0
V0LTAGE_TRI[0] => TEMP[0].DATAIN
V0LTAGE_TRI[0] => Equal0.IN15
V0LTAGE_TRI[1] => TEMP[1].DATAIN
V0LTAGE_TRI[1] => Equal0.IN14
V0LTAGE_TRI[2] => TEMP[2].DATAIN
V0LTAGE_TRI[2] => Equal0.IN13
V0LTAGE_TRI[3] => TEMP[3].DATAIN
V0LTAGE_TRI[3] => Equal0.IN12
V0LTAGE_TRI[4] => TEMP[4].DATAIN
V0LTAGE_TRI[4] => Equal0.IN11
V0LTAGE_TRI[5] => TEMP[5].DATAIN
V0LTAGE_TRI[5] => Equal0.IN10
V0LTAGE_TRI[6] => TEMP[6].DATAIN
V0LTAGE_TRI[6] => Equal0.IN9
V0LTAGE_TRI[7] => TEMP[7].DATAIN
V0LTAGE_TRI[7] => Equal0.IN8
EN <= EN~0.DB_MAX_OUTPUT_PORT_TYPE
TRIGGER <= EN~0.DB_MAX_OUTPUT_PORT_TYPE


|SCANWAVE|GET_RDADDR:inst10
CLK => COUNTER[11].CLK
CLK => COUNTER[10].CLK
CLK => COUNTER[9].CLK
CLK => COUNTER[8].CLK
CLK => COUNTER[7].CLK
CLK => COUNTER[6].CLK
CLK => COUNTER[5].CLK
CLK => COUNTER[4].CLK
CLK => COUNTER[3].CLK
CLK => COUNTER[2].CLK
CLK => COUNTER[1].CLK
CLK => COUNTER[0].CLK
CLR => COUNTER[11].ACLR
CLR => COUNTER[10].ALOAD
CLR => COUNTER[9].ALOAD
CLR => COUNTER[8].ALOAD
CLR => COUNTER[7].ALOAD
CLR => COUNTER[6].ALOAD
CLR => COUNTER[5].ALOAD
CLR => COUNTER[4].ALOAD
CLR => COUNTER[3].ALOAD
CLR => COUNTER[2].ALOAD
CLR => COUNTER[1].ALOAD
CLR => COUNTER[0].ALOAD
PHASE[0] => COUNTER[0].ADATA
PHASE[1] => COUNTER[1].ADATA
PHASE[2] => COUNTER[2].ADATA
PHASE[3] => COUNTER[3].ADATA
PHASE[4] => COUNTER[4].ADATA
PHASE[5] => COUNTER[5].ADATA
PHASE[6] => COUNTER[6].ADATA
PHASE[7] => COUNTER[7].ADATA
PHASE[8] => COUNTER[8].ADATA
PHASE[9] => COUNTER[9].ADATA
PHASE[10] => COUNTER[10].ADATA
Q[0] <= COUNTER[0].DB_MAX_OUTPUT_PORT_TYPE
Q[1] <= COUNTER[1].DB_MAX_OUTPUT_PORT_TYPE
Q[2] <= COUNTER[2].DB_MAX_OUTPUT_PORT_TYPE
Q[3] <= COUNTER[3].DB_MAX_OUTPUT_PORT_TYPE
Q[4] <= COUNTER[4].DB_MAX_OUTPUT_PORT_TYPE
Q[5] <= COUNTER[5].DB_MAX_OUTPUT_PORT_TYPE
Q[6] <= COUNTER[6].DB_MAX_OUTPUT_PORT_TYPE
Q[7] <= COUNTER[7].DB_MAX_OUTPUT_PORT_TYPE
Q[8] <= COUNTER[8].DB_MAX_OUTPUT_PORT_TYPE
Q[9] <= COUNTER[9].DB_MAX_OUTPUT_PORT_TYPE
Q[10] <= COUNTER[10].DB_MAX_OUTPUT_PORT_TYPE


|SCANWAVE|generator_accB:inst4
CLK => REG_Q[21].CLK
CLK => REG_Q[20].CLK
CLK => REG_Q[19].CLK
CLK => REG_Q[18].CLK
CLK => REG_Q[17].CLK
CLK => REG_Q[16].CLK
CLK => REG_Q[15].CLK
CLK => REG_Q[14].CLK
CLK => REG_Q[13].CLK
CLK => REG_Q[12].CLK
CLK => REG_Q[11].CLK
CLK => REG_Q[10].CLK
CLK => REG_Q[9].CLK
CLK => REG_Q[8].CLK
CLK => REG_Q[7].CLK
CLK => REG_Q[6].CLK
CLK => REG_Q[5].CLK
CLK => REG_Q[4].CLK
CLK => REG_Q[3].CLK
CLK => REG_Q[2].CLK
CLK => REG_Q[1].CLK
CLK => REG_Q[0].CLK
CLK => START~reg0.CLK
CLK => TEMP.CLK
CLR => REG_Q[21].ACLR
CLR => REG_Q[20].ACLR
CLR => REG_Q[19].ACLR
CLR => REG_Q[18].ACLR
CLR => REG_Q[17].ACLR
CLR => REG_Q[16].ACLR
CLR => REG_Q[15].ACLR
CLR => REG_Q[14].ACLR
CLR => REG_Q[13].ACLR
CLR => REG_Q[12].ACLR
CLR => REG_Q[11].ACLR
CLR => REG_Q[10].ACLR
CLR => REG_Q[9].ACLR
CLR => REG_Q[8].ACLR
CLR => REG_Q[7].ACLR
CLR => REG_Q[6].ACLR
CLR => REG_Q[5].ACLR
CLR => REG_Q[4].ACLR
CLR => REG_Q[3].ACLR
CLR => REG_Q[2].ACLR
CLR => REG_Q[1].ACLR
CLR => REG_Q[0].ACLR
CLR => START~reg0.ENA
CLR => TEMP.ENA
A[0] => Add0.IN22
A[1] => Add0.IN21
A[2] => Add0.IN20
A[3] => Add0.IN19
A[4] => Add0.IN18
A[5] => Add0.IN17
A[6] => Add0.IN16
A[7] => Add0.IN15
A[8] => Add0.IN14
A[9] => Add0.IN13
A[10] => Add0.IN12
A[11] => Add0.IN11
A[12] => Add0.IN10
A[13] => Add0.IN9
A[14] => Add0.IN8
A[15] => Add0.IN7
A[16] => Add0.IN6
A[17] => Add0.IN5
A[18] => Add0.IN4
A[19] => Add0.IN3
A[20] => Add0.IN2
A[21] => Add0.IN1
START <= START~reg0.DB_MAX_OUTPUT_PORT_TYPE
SEL <= TEMP.DB_MAX_OUTPUT_PORT_TYPE
Q[0] <= REG_Q[14].DB_MAX_OUTPUT_PORT_TYPE
Q[1] <= REG_Q[15].DB_MAX_OUTPUT_PORT_TYPE
Q[2] <= REG_Q[16].DB_MAX_OUTPUT_PORT_TYPE
Q[3] <= REG_Q[17].DB_MAX_OUTPUT_PORT_TYPE
Q[4] <= REG_Q[18].DB_MAX_OUTPUT_PORT_TYPE
Q[5] <= REG_Q[19].DB_MAX_OUTPUT_PORT_TYPE
Q[6] <= REG_Q[20].DB_MAX_OUTPUT_PORT_TYPE
Q[7] <= REG_Q[21].DB_MAX_OUTPUT_PORT_TYPE


|SCANWAVE|FREDEVIDER8:inst8
CLKIN => COUNTER[2].CLK
CLKIN => COUNTER[1].CLK
CLKIN => COUNTER[0].CLK
CLKIN => CLK.CLK
CLKOUT <= CLK.DB_MAX_OUTPUT_PORT_TYPE


|SCANWAVE|bustri:inst1
data[0] => lpm_bustri:lpm_bustri_component.data[0]
data[1] => lpm_bustri:lpm_bustri_component.data[1]
data[2] => lpm_bustri:lpm_bustri_component.data[2]
data[3] => lpm_bustri:lpm_bustri_component.data[3]
data[4] => lpm_bustri:lpm_bustri_component.data[4]
data[5] => lpm_bustri:lpm_bustri_component.data[5]
data[6] => lpm_bustri:lpm_bustri_component.data[6]
data[7] => lpm_bustri:lpm_bustri_component.data[7]
enabledt => lpm_bustri:lpm_bustri_component.enabledt
enabletr => lpm_bustri:lpm_bustri_component.enabletr
tridata[0] <= lpm_bustri:lpm_bustri_component.tridata[0]
tridata[1] <= lpm_bustri:lpm_bustri_component.tridata[1]
tridata[2] <= lpm_bustri:lpm_bustri_component.tridata[2]
tridata[3] <= lpm_bustri:lpm_bustri_component.tridata[3]
tridata[4] <= lpm_bustri:lpm_bustri_component.tridata[4]
tridata[5] <= lpm_bustri:lpm_bustri_component.tridata[5]
tridata[6] <= lpm_bustri:lpm_bustri_component.tridata[6]
tridata[7] <= lpm_bustri:lpm_bustri_component.tridata[7]
result[0] <= lpm_bustri:lpm_bustri_component.result[0]
result[1] <= lpm_bustri:lpm_bustri_component.result[1]
result[2] <= lpm_bustri:lpm_bustri_component.result[2]
result[3] <= lpm_bustri:lpm_bustri_component.result[3]
result[4] <= lpm_bustri:lpm_bustri_component.result[4]
result[5] <= lpm_bustri:lpm_bustri_component.result[5]
result[6] <= lpm_bustri:lpm_bustri_component.result[6]
result[7] <= lpm_bustri:lpm_bustri_component.result[7]


|SCANWAVE|bustri:inst1|lpm_bustri:lpm_bustri_component
tridata[0] <= dout[0]
tridata[1] <= dout[1]
tridata[2] <= dout[2]