scanwave.hier_info

数字示波器的FPGA实现 VHDL编写 Quartus7.1测试通过

QL[3] => P0_OUT~20.DATAB
QL[4] => P0_OUT~19.DATAB
QL[5] => P0_OUT~18.DATAB
QL[6] => P0_OUT~17.DATAB
QL[7] => P0_OUT~16.DATAB
AMPL[0] => P0_OUT~7.DATAB
AMPL[1] => P0_OUT~6.DATAB
AMPL[2] => P0_OUT~5.DATAB
AMPL[3] => P0_OUT~4.DATAB
AMPL[4] => P0_OUT~3.DATAB
AMPL[5] => P0_OUT~2.DATAB
AMPL[6] => P0_OUT~1.DATAB
AMPL[7] => P0_OUT~0.DATAB


|SCANWAVE|AMPL_COUNT:inst2
CLKIN => COUNT[11].CLK
CLKIN => COUNT[10].CLK
CLKIN => COUNT[9].CLK
CLKIN => COUNT[8].CLK
CLKIN => COUNT[7].CLK
CLKIN => COUNT[6].CLK
CLKIN => COUNT[5].CLK
CLKIN => COUNT[4].CLK
CLKIN => COUNT[3].CLK
CLKIN => COUNT[2].CLK
CLKIN => COUNT[1].CLK
CLKIN => COUNT[0].CLK
CLKIN => MAX[7].CLK
CLKIN => MAX[6].CLK
CLKIN => MAX[5].CLK
CLKIN => MAX[4].CLK
CLKIN => MAX[3].CLK
CLKIN => MAX[2].CLK
CLKIN => MAX[1].CLK
CLKIN => MAX[0].CLK
CLKIN => MIN[7].CLK
CLKIN => MIN[6].CLK
CLKIN => MIN[5].CLK
CLKIN => MIN[4].CLK
CLKIN => MIN[3].CLK
CLKIN => MIN[2].CLK
CLKIN => MIN[1].CLK
CLKIN => MIN[0].CLK
CLKIN => Q[7]~reg0.CLK
CLKIN => Q[6]~reg0.CLK
CLKIN => Q[5]~reg0.CLK
CLKIN => Q[4]~reg0.CLK
CLKIN => Q[3]~reg0.CLK
CLKIN => Q[2]~reg0.CLK
CLKIN => Q[1]~reg0.CLK
CLKIN => Q[0]~reg0.CLK
AIN[0] => MIN~7.DATAB
AIN[0] => LessThan2.IN8
AIN[0] => MAX~7.DATAB
AIN[0] => LessThan1.IN8
AIN[1] => MIN~6.DATAB
AIN[1] => LessThan2.IN7
AIN[1] => MAX~6.DATAB
AIN[1] => LessThan1.IN7
AIN[2] => MIN~5.DATAB
AIN[2] => LessThan2.IN6
AIN[2] => MAX~5.DATAB
AIN[2] => LessThan1.IN6
AIN[3] => MIN~4.DATAB
AIN[3] => LessThan2.IN5
AIN[3] => MAX~4.DATAB
AIN[3] => LessThan1.IN5
AIN[4] => MIN~3.DATAB
AIN[4] => LessThan2.IN4
AIN[4] => MAX~3.DATAB
AIN[4] => LessThan1.IN4
AIN[5] => MIN~2.DATAB
AIN[5] => LessThan2.IN3
AIN[5] => MAX~2.DATAB
AIN[5] => LessThan1.IN3
AIN[6] => MIN~1.DATAB
AIN[6] => LessThan2.IN2
AIN[6] => MAX~1.DATAB
AIN[6] => LessThan1.IN2
AIN[7] => MIN~0.DATAB
AIN[7] => LessThan2.IN1
AIN[7] => MAX~0.DATAB
AIN[7] => LessThan1.IN1
CLR => COUNT[11].ACLR
CLR => COUNT[10].ACLR
CLR => COUNT[9].ACLR
CLR => COUNT[8].ACLR
CLR => COUNT[7].ACLR
CLR => COUNT[6].ACLR
CLR => COUNT[5].ACLR
CLR => COUNT[4].ACLR
CLR => COUNT[3].ACLR
CLR => COUNT[2].ACLR
CLR => COUNT[1].ACLR
CLR => COUNT[0].ACLR
CLR => MAX[7].ACLR
CLR => MAX[6].ACLR
CLR => MAX[5].ACLR
CLR => MAX[4].ACLR
CLR => MAX[3].ACLR
CLR => MAX[2].ACLR
CLR => MAX[1].ACLR
CLR => MAX[0].ACLR
CLR => MIN[7].PRESET
CLR => MIN[6].PRESET
CLR => MIN[5].PRESET
CLR => MIN[4].PRESET
CLR => MIN[3].PRESET
CLR => MIN[2].PRESET
CLR => MIN[1].PRESET
CLR => MIN[0].PRESET
CLR => Q[0]~reg0.ENA
CLR => Q[7]~reg0.ENA
CLR => Q[6]~reg0.ENA
CLR => Q[5]~reg0.ENA
CLR => Q[4]~reg0.ENA
CLR => Q[3]~reg0.ENA
CLR => Q[2]~reg0.ENA
CLR => Q[1]~reg0.ENA
Q[0] <= Q[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
Q[1] <= Q[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
Q[2] <= Q[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
Q[3] <= Q[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
Q[4] <= Q[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
Q[5] <= Q[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
Q[6] <= Q[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
Q[7] <= Q[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE


|SCANWAVE|FREDEVIDER2:inst13
CLKIN => CLK.CLK
CLKOUT <= CLK.DB_MAX_OUTPUT_PORT_TYPE


|SCANWAVE|dram:inst
data[0] => altsyncram:altsyncram_component.data_a[0]
data[1] => altsyncram:altsyncram_component.data_a[1]
data[2] => altsyncram:altsyncram_component.data_a[2]
data[3] => altsyncram:altsyncram_component.data_a[3]
data[4] => altsyncram:altsyncram_component.data_a[4]
data[5] => altsyncram:altsyncram_component.data_a[5]
data[6] => altsyncram:altsyncram_component.data_a[6]
data[7] => altsyncram:altsyncram_component.data_a[7]
wren => altsyncram:altsyncram_component.wren_a
wraddress[0] => altsyncram:altsyncram_component.address_a[0]
wraddress[1] => altsyncram:altsyncram_component.address_a[1]
wraddress[2] => altsyncram:altsyncram_component.address_a[2]
wraddress[3] => altsyncram:altsyncram_component.address_a[3]
wraddress[4] => altsyncram:altsyncram_component.address_a[4]
wraddress[5] => altsyncram:altsyncram_component.address_a[5]
wraddress[6] => altsyncram:altsyncram_component.address_a[6]
wraddress[7] => altsyncram:altsyncram_component.address_a[7]
wraddress[8] => altsyncram:altsyncram_component.address_a[8]
wraddress[9] => altsyncram:altsyncram_component.address_a[9]
wraddress[10] => altsyncram:altsyncram_component.address_a[10]
rdaddress[0] => altsyncram:altsyncram_component.address_b[0]
rdaddress[1] => altsyncram:altsyncram_component.address_b[1]
rdaddress[2] => altsyncram:altsyncram_component.address_b[2]
rdaddress[3] => altsyncram:altsyncram_component.address_b[3]
rdaddress[4] => altsyncram:altsyncram_component.address_b[4]
rdaddress[5] => altsyncram:altsyncram_component.address_b[5]
rdaddress[6] => altsyncram:altsyncram_component.address_b[6]
rdaddress[7] => altsyncram:altsyncram_component.address_b[7]
rdaddress[8] => altsyncram:altsyncram_component.address_b[8]
rdaddress[9] => altsyncram:altsyncram_component.address_b[9]
rdaddress[10] => altsyncram:altsyncram_component.address_b[10]
wrclock => altsyncram:altsyncram_component.clock0
rdclock => altsyncram:altsyncram_component.clock1
q[0] <= altsyncram:altsyncram_component.q_b[0]
q[1] <= altsyncram:altsyncram_component.q_b[1]
q[2] <= altsyncram:altsyncram_component.q_b[2]
q[3] <= altsyncram:altsyncram_component.q_b[3]
q[4] <= altsyncram:altsyncram_component.q_b[4]
q[5] <= altsyncram:altsyncram_component.q_b[5]
q[6] <= altsyncram:altsyncram_component.q_b[6]
q[7] <= altsyncram:altsyncram_component.q_b[7]


|SCANWAVE|dram:inst|altsyncram:altsyncram_component
wren_a => altsyncram_fbg1:auto_generated.wren_a
rden_a => ~NO_FANOUT~
wren_b => ~NO_FANOUT~
rden_b => ~NO_FANOUT~
data_a[0] => altsyncram_fbg1:auto_generated.data_a[0]
data_a[1] => altsyncram_fbg1:auto_generated.data_a[1]
data_a[2] => altsyncram_fbg1:auto_generated.data_a[2]
data_a[3] => altsyncram_fbg1:auto_generated.data_a[3]
data_a[4] => altsyncram_fbg1:auto_generated.data_a[4]
data_a[5] => altsyncram_fbg1:auto_generated.data_a[5]
data_a[6] => altsyncram_fbg1:auto_generated.data_a[6]
data_a[7] => altsyncram_fbg1:auto_generated.data_a[7]
data_b[0] => ~NO_FANOUT~
data_b[1] => ~NO_FANOUT~
data_b[2] => ~NO_FANOUT~
data_b[3] => ~NO_FANOUT~
data_b[4] => ~NO_FANOUT~
data_b[5] => ~NO_FANOUT~
data_b[6] => ~NO_FANOUT~
data_b[7] => ~NO_FANOUT~
address_a[0] => altsyncram_fbg1:auto_generated.address_a[0]
address_a[1] => altsyncram_fbg1:auto_generated.address_a[1]
address_a[2] => altsyncram_fbg1:auto_generated.address_a[2]
address_a[3] => altsyncram_fbg1:auto_generated.address_a[3]
address_a[4] => altsyncram_fbg1:auto_generated.address_a[4]
address_a[5] => altsyncram_fbg1:auto_generated.address_a[5]
address_a[6] => altsyncram_fbg1:auto_generated.address_a[6]
address_a[7] => altsyncram_fbg1:auto_generated.address_a[7]
address_a[8] => altsyncram_fbg1:auto_generated.address_a[8]
address_a[9] => altsyncram_fbg1:auto_generated.address_a[9]
address_a[10] => altsyncram_fbg1:auto_generated.address_a[10]
address_b[0] => altsyncram_fbg1:auto_generated.address_b[0]
address_b[1] => altsyncram_fbg1:auto_generated.address_b[1]
address_b[2] => altsyncram_fbg1:auto_generated.address_b[2]
address_b[3] => altsyncram_fbg1:auto_generated.address_b[3]
address_b[4] => altsyncram_fbg1:auto_generated.address_b[4]
address_b[5] => altsyncram_fbg1:auto_generated.address_b[5]
address_b[6] => altsyncram_fbg1:auto_generated.address_b[6]
address_b[7] => altsyncram_fbg1:auto_generated.address_b[7]
address_b[8] => altsyncram_fbg1:auto_generated.address_b[8]
address_b[9] => altsyncram_fbg1:auto_generated.address_b[9]
address_b[10] => altsyncram_fbg1:auto_generated.address_b[10]
addressstall_a => ~NO_FANOUT~
addressstall_b => ~NO_FANOUT~
clock0 => altsyncram_fbg1:auto_generated.clock0
clock1 => altsyncram_fbg1:auto_generated.clock1
clocken0 => ~NO_FANOUT~
clocken1 => ~NO_FANOUT~
clocken2 => ~NO_FANOUT~
clocken3 => ~NO_FANOUT~
aclr0 => ~NO_FANOUT~
aclr1 => ~NO_FANOUT~
byteena_a[0] => ~NO_FANOUT~
byteena_b[0] => ~NO_FANOUT~
q_a[0] <= <GND>
q_a[1] <= <GND>
q_a[2] <= <GND>
q_a[3] <= <GND>
q_a[4] <= <GND>
q_a[5] <= <GND>
q_a[6] <= <GND>
q_a[7] <= <GND>
q_b[0] <= altsyncram_fbg1:auto_generated.q_b[0]
q_b[1] <= altsyncram_fbg1:auto_generated.q_b[1]
q_b[2] <= altsyncram_fbg1:auto_generated.q_b[2]
q_b[3] <= altsyncram_fbg1:auto_generated.q_b[3]
q_b[4] <= altsyncram_fbg1:auto_generated.q_b[4]
q_b[5] <= altsyncram_fbg1:auto_generated.q_b[5]
q_b[6] <= altsyncram_fbg1:auto_generated.q_b[6]
q_b[7] <= altsyncram_fbg1:auto_generated.q_b[7]
eccstatus[0] <= <GND>
eccstatus[1] <= <GND>
eccstatus[2] <= <GND>


|SCANWAVE|dram:inst|altsyncram:altsyncram_component|altsyncram_fbg1:auto_generated
address_a[0] => ram_block1a0.PORTAADDR
address_a[0] => ram_block1a1.PORTAADDR
address_a[0] => ram_block1a2.PORTAADDR
address_a[0] => ram_block1a3.PORTAADDR
address_a[0] => ram_block1a4.PORTAADDR
address_a[0] => ram_block1a5.PORTAADDR
address_a[0] => ram_block1a6.PORTAADDR
address_a[0] => ram_block1a7.PORTAADDR
address_a[1] => ram_block1a0.PORTAADDR1
address_a[1] => ram_block1a1.PORTAADDR1
address_a[1] => ram_block1a2.PORTAADDR1
address_a[1] => ram_block1a3.PORTAADDR1
address_a[1] => ram_block1a4.PORTAADDR1
address_a[1] => ram_block1a5.PORTAADDR1
address_a[1] => ram_block1a6.PORTAADDR1
address_a[1] => ram_block1a7.PORTAADDR1
address_a[2] => ram_block1a0.PORTAADDR2
address_a[2] => ram_block1a1.PORTAADDR2
address_a[2] => ram_block1a2.PORTAADDR2
address_a[2] => ram_block1a3.PORTAADDR2
address_a[2] => ram_block1a4.PORTAADDR2
address_a[2] => ram_block1a5.PORTAADDR2
address_a[2] => ram_block1a6.PORTAADDR2
address_a[2] => ram_block1a7.PORTAADDR2
address_a[3] => ram_block1a0.PORTAADDR3
address_a[3] => ram_block1a1.PORTAADDR3
address_a[3] => ram_block1a2.PORTAADDR3
address_a[3] => ram_block1a3.PORTAADDR3
address_a[3] => ram_block1a4.PORTAADDR3
address_a[3] => ram_block1a5.PORTAADDR3
address_a[3] => ram_block1a6.PORTAADDR3
address_a[3] => ram_block1a7.PORTAADDR3
address_a[4] => ram_block1a0.PORTAADDR4
address_a[4] => ram_block1a1.PORTAADDR4
address_a[4] => ram_block1a2.PORTAADDR4
address_a[4] => ram_block1a3.PORTAADDR4
address_a[4] => ram_block1a4.PORTAADDR4
address_a[4] => ram_block1a5.PORTAADDR4
address_a[4] => ram_block1a6.PORTAADDR4
address_a[4] => ram_block1a7.PORTAADDR4
address_a[5] => ram_block1a0.PORTAADDR5
address_a[5] => ram_block1a1.PORTAADDR5
address_a[5] => ram_block1a2.PORTAADDR5
address_a[5] => ram_block1a3.PORTAADDR5
address_a[5] => ram_block1a4.PORTAADDR5
address_a[5] => ram_block1a5.PORTAADDR5
address_a[5] => ram_block1a6.PORTAADDR5
address_a[5] => ram_block1a7.PORTAADDR5
address_a[6] => ram_block1a0.PORTAADDR6
address_a[6] => ram_block1a1.PORTAADDR6
address_a[6] => ram_block1a2.PORTAADDR6
address_a[6] => ram_block1a3.PORTAADDR6
address_a[6] => ram_block1a4.PORTAADDR6
address_a[6] => ram_block1a5.PORTAADDR6
address_a[6] => ram_block1a6.PORTAADDR6
address_a[6] => ram_block1a7.PORTAADDR6
address_a[7] => ram_block1a0.PORTAADDR7
address_a[7] => ram_block1a1.PORTAADDR7
address_a[7] => ram_block1a2.PORTAADDR7
address_a[7] => ram_block1a3.PORTAADDR7
address_a[7] => ram_block1a4.PORTAADDR7
address_a[7] => ram_block1a5.PORTAADDR7
address_a[7] => ram_block1a6.PORTAADDR7
address_a[7] => ram_block1a7.PORTAADDR7
address_a[8] => ram_block1a0.PORTAADDR8
address_a[8] => ram_block1a1.PORTAADDR8
address_a[8] => ram_block1a2.PORTAADDR8
address_a[8] => ram_block1a3.PORTAADDR8
address_a[8] => ram_block1a4.PORTAADDR8
address_a[8] => ram_block1a5.PORTAADDR8
address_a[8] => ram_block1a6.PORTAADDR8
address_a[8] => ram_block1a7.PORTAADDR8
address_a[9] => ram_block1a0.PORTAADDR9
address_a[9] => ram_block1a1.PORTAADDR9
address_a[9] => ram_block1a2.PORTAADDR9
address_a[9] => ram_block1a3.PORTAADDR9
address_a[9] => ram_block1a4.PORTAADDR9
address_a[9] => ram_block1a5.PORTAADDR9
address_a[9] => ram_block1a6.PORTAADDR9
address_a[9] => ram_block1a7.PORTAADDR9
address_a[10] => ram_block1a0.PORTAADDR10
address_a[10] => ram_block1a1.PORTAADDR10
address_a[10] => ram_block1a2.PORTAADDR10
address_a[10] => ram_block1a3.PORTAADDR10
address_a[10] => ram_block1a4.PORTAADDR10
address_a[10] => ram_block1a5.PORTAADDR10
address_a[10] => ram_block1a6.PORTAADDR10
address_a[10] => ram_block1a7.PORTAADDR10
address_b[0] => ram_block1a0.PORTBADDR
address_b[0] => ram_block1a1.PORTBADDR
address_b[0] => ram_block1a2.PORTBADDR
address_b[0] => ram_block1a3.PORTBADDR
address_b[0] => ram_block1a4.PORTBADDR
address_b[0] => ram_block1a5.PORTBADDR
address_b[0] => ram_block1a6.PORTBADDR
address_b[0] => ram_block1a7.PORTBADDR
address_b[1] => ram_block1a0.PORTBADDR1
address_b[1] => ram_block1a1.PORTBADDR1
address_b[1] => ram_block1a2.PORTBADDR1
address_b[1] => ram_block1a3.PORTBADDR1
address_b[1] => ram_block1a4.PORTBADDR1
address_b[1] => ram_block1a5.PORTBADDR1
address_b[1] => ram_block1a6.PORTBADDR1
address_b[1] => ram_block1a7.PORTBADDR1
address_b[2] => ram_block1a0.PORTBADDR2
address_b[2] => ram_block1a1.PORTBADDR2
address_b[2] => ram_block1a2.PORTBADDR2
address_b[2] => ram_block1a3.PORTBADDR2
address_b[2] => ram_block1a4.PORTBADDR2
address_b[2] => ram_block1a5.PORTBADDR2
address_b[2] => ram_block1a6.PORTBADDR2
address_b[2] => ram_block1a7.PORTBADDR2
address_b[3] => ram_block1a0.PORTBADDR3
address_b[3] => ram_block1a1.PORTBADDR3
address_b[3] => ram_block1a2.PORTBADDR3
address_b[3] => ram_block1a3.PORTBADDR3
address_b[3] => ram_block1a4.PORTBADDR3
address_b[3] => ram_block1a5.PORTBADDR3
address_b[3] => ram_block1a6.PORTBADDR3
address_b[3] => ram_block1a7.PORTBADDR3
address_b[4] => ram_block1a0.PORTBADDR4
address_b[4] => ram_block1a1.PORTBADDR4
address_b[4] => ram_block1a2.PORTBADDR4
address_b[4] => ram_block1a3.PORTBADDR4
address_b[4] => ram_block1a4.PORTBADDR4
address_b[4] => ram_block1a5.PORTBADDR4
address_b[4] => ram_block1a6.PORTBADDR4
address_b[4] => ram_block1a7.PORTBADDR4
address_b[5] => ram_block1a0.PORTBADDR5
address_b[5] => ram_block1a1.PORTBADDR5
address_b[5] => ram_block1a2.PORTBADDR5
address_b[5] => ram_block1a3.PORTBADDR5
address_b[5] => ram_block1a4.PORTBADDR5
address_b[5] => ram_block1a5.PORTBADDR5
address_b[5] => ram_block1a6.PORTBADDR5
address_b[5] => ram_block1a7.PORTBADDR5
address_b[6] => ram_block1a0.PORTBADDR6
address_b[6] => ram_block1a1.PORTBADDR6
address_b[6] => ram_block1a2.PORTBADDR6
address_b[6] => ram_block1a3.PORTBADDR6
address_b[6] => ram_block1a4.PORTBADDR6
address_b[6] => ram_block1a5.PORTBADDR6