📄 test.hif

📁 数字示波器的FPGA实现 VHDL编写 Quartus7.1测试通过
💻 HIF
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data_a1
data_a2
data_a3
data_a4
data_a5
data_a6
data_a7
q_b0
q_b1
q_b2
q_b3
q_b4
q_b5
q_b6
q_b7
wren_a
}
# include_file {
c:|altera|quartus41|libraries|megafunctions|stratix_ram_block.inc
1081479498
c:|altera|quartus41|libraries|megafunctions|lpm_mux.inc
1081478758
c:|altera|quartus41|libraries|megafunctions|lpm_decode.inc
1081478592
c:|altera|quartus41|libraries|megafunctions|aglobal41.inc
1088009406
c:|altera|quartus41|libraries|megafunctions|altsyncram.inc
1081477654
c:|altera|quartus41|libraries|megafunctions|a_rdenreg.inc
1081476578
c:|altera|quartus41|libraries|megafunctions|altrom.inc
1081477590
c:|altera|quartus41|libraries|megafunctions|altram.inc
1081477560
c:|altera|quartus41|libraries|megafunctions|altdpram.inc
1081477328
c:|altera|quartus41|libraries|megafunctions|altqpram.inc
1081477546
}
# end
# entity
FREDEVIDER8
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
FREDEVIDER8.vhd
1123129388
4
# storage
db|test.(17).cnf
db|test.(17).cnf
# internal_option {
AUTO_RESOURCE_SHARING
OFF
PRESERVE_REGISTER
OFF
DUP_REG_EXTRACTION
ON
DUP_LOGIC_EXTRACTION
ON
VHDL_VERILOG_BREAK_LOOPS
OFF
}
# end
# entity
altsyncram
# case_insensitive
# source_file
c:|altera|quartus41|libraries|megafunctions|altsyncram.tdf
1088009418
6
# storage
db|test.(18).cnf
db|test.(18).cnf
# user_parameter {
BYTE_SIZE_BLOCK
8
PARAMETER_UNKNOWN
DEF
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
OPERATION_MODE
ROM
PARAMETER_UNKNOWN
USR
WIDTH_A
6
PARAMETER_UNKNOWN
USR
WIDTHAD_A
8
PARAMETER_UNKNOWN
USR
NUMWORDS_A
256
PARAMETER_UNKNOWN
USR
OUTDATA_REG_A
UNREGISTERED
PARAMETER_UNKNOWN
USR
ADDRESS_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
OUTDATA_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
WRCONTROL_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
INDATA_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
BYTEENA_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
WIDTH_B
1
PARAMETER_UNKNOWN
DEF
WIDTHAD_B
1
PARAMETER_UNKNOWN
DEF
NUMWORDS_B
1
PARAMETER_UNKNOWN
DEF
INDATA_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
WRCONTROL_WRADDRESS_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
RDCONTROL_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
ADDRESS_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
OUTDATA_REG_B
UNREGISTERED
PARAMETER_UNKNOWN
DEF
BYTEENA_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
INDATA_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
WRCONTROL_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
ADDRESS_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
OUTDATA_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
RDCONTROL_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
BYTEENA_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
WIDTH_BYTEENA_A
1
PARAMETER_UNKNOWN
DEF
WIDTH_BYTEENA_B
1
PARAMETER_UNKNOWN
DEF
RAM_BLOCK_TYPE
AUTO
PARAMETER_UNKNOWN
DEF
BYTE_SIZE
8
PARAMETER_UNKNOWN
DEF
READ_DURING_WRITE_MODE_MIXED_PORTS
DONT_CARE
PARAMETER_UNKNOWN
DEF
INIT_FILE
test_AD0.rtl.mif
PARAMETER_UNKNOWN
USR
INIT_FILE_LAYOUT
PORT_A
PARAMETER_UNKNOWN
DEF
MAXIMUM_DEPTH
0
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_INPUT_A
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_INPUT_B
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_OUTPUT_A
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_OUTPUT_B
NORMAL
PARAMETER_UNKNOWN
DEF
DEVICE_FAMILY
Cyclone
PARAMETER_UNKNOWN
USR
CBXI_PARAMETER
altsyncram_m8j
PARAMETER_UNKNOWN
USR
}
# used_port {
address_a0
address_a1
address_a2
address_a3
address_a4
address_a5
address_a6
address_a7
clock0
q_a0
q_a1
q_a2
q_a3
q_a4
q_a5
}
# include_file {
c:|altera|quartus41|libraries|megafunctions|stratix_ram_block.inc
1081479498
c:|altera|quartus41|libraries|megafunctions|lpm_mux.inc
1081478758
c:|altera|quartus41|libraries|megafunctions|lpm_decode.inc
1081478592
c:|altera|quartus41|libraries|megafunctions|aglobal41.inc
1088009406
c:|altera|quartus41|libraries|megafunctions|altsyncram.inc
1081477654
c:|altera|quartus41|libraries|megafunctions|a_rdenreg.inc
1081476578
c:|altera|quartus41|libraries|megafunctions|altrom.inc
1081477590
c:|altera|quartus41|libraries|megafunctions|altram.inc
1081477560
c:|altera|quartus41|libraries|megafunctions|altdpram.inc
1081477328
c:|altera|quartus41|libraries|megafunctions|altqpram.inc
1081477546
}
# end
# entity
BUS_1
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
BUS_1.vhd
1123572644
4
# storage
db|TEST.(3).cnf
db|TEST.(3).cnf
# internal_option {
AUTO_RESOURCE_SHARING
OFF
PRESERVE_REGISTER
OFF
DUP_REG_EXTRACTION
ON
DUP_LOGIC_EXTRACTION
ON
VHDL_VERILOG_BREAK_LOOPS
OFF
}
# end
# entity
test
# case_insensitive
# source_file
test.bdf
1123638276
23
# storage
db|TEST.(1).cnf
db|TEST.(1).cnf
# end
# entity
BUSTRI
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
BUSTRI.vhd
1123638234
4
# storage
db|TEST.(11).cnf
db|TEST.(11).cnf
# internal_option {
AUTO_RESOURCE_SHARING
OFF
PRESERVE_REGISTER
OFF
DUP_REG_EXTRACTION
ON
DUP_LOGIC_EXTRACTION
ON
VHDL_VERILOG_BREAK_LOOPS
OFF
}
# end
# entity
altsyncram_8r81
# case_insensitive
# source_file
db|altsyncram_8r81.tdf
1123555710
6
# storage
db|TEST.(15).cnf
db|TEST.(15).cnf
# used_port {
wren_a
data_a0
data_a1
data_a2
data_a3
data_a4
data_a5
data_a6
data_a7
address_a0
address_a1
address_a2
address_a3
address_a4
address_a5
address_a6
address_a7
address_a8
address_a9
address_a10
address_b0
address_b1
address_b2
address_b3
address_b4
address_b5
address_b6
address_b7
address_b8
address_b9
address_b10
clock0
clock1
q_b0
q_b1
q_b2
q_b3
q_b4
q_b5
q_b6
q_b7
}
# memory_file {
none
0
}
# end
# entity
generator_accB
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
generator_accb.vhd
1123637162
4
# storage
db|TEST.(16).cnf
db|TEST.(16).cnf
# internal_option {
AUTO_RESOURCE_SHARING
OFF
PRESERVE_REGISTER
OFF
DUP_REG_EXTRACTION
ON
DUP_LOGIC_EXTRACTION
ON
VHDL_VERILOG_BREAK_LOOPS
OFF
}
# end
# entity
generator_add
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
GENERATOR_ADD.vhd
1123637288
4
# storage
db|TEST.(19).cnf
db|TEST.(19).cnf
# internal_option {
AUTO_RESOURCE_SHARING
OFF
PRESERVE_REGISTER
OFF
DUP_REG_EXTRACTION
ON
DUP_LOGIC_EXTRACTION
ON
VHDL_VERILOG_BREAK_LOOPS
OFF
}
# end
# entity
altsyncram
# case_insensitive
# source_file
c:|altera|quartus41|libraries|megafunctions|altsyncram.tdf
1088009418
6
# storage
db|TEST.(20).cnf
db|TEST.(20).cnf
# user_parameter {
BYTE_SIZE_BLOCK
8
PARAMETER_UNKNOWN
DEF
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
OPERATION_MODE
ROM
PARAMETER_UNKNOWN
USR
WIDTH_A
7
PARAMETER_UNKNOWN
USR
WIDTHAD_A
8
PARAMETER_UNKNOWN
USR
NUMWORDS_A
256
PARAMETER_UNKNOWN
USR
OUTDATA_REG_A
UNREGISTERED
PARAMETER_UNKNOWN
USR
ADDRESS_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
OUTDATA_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
WRCONTROL_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
INDATA_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
BYTEENA_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
WIDTH_B
1
PARAMETER_UNKNOWN
DEF
WIDTHAD_B
1
PARAMETER_UNKNOWN
DEF
NUMWORDS_B
1
PARAMETER_UNKNOWN
DEF
INDATA_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
WRCONTROL_WRADDRESS_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
RDCONTROL_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
ADDRESS_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
OUTDATA_REG_B
UNREGISTERED
PARAMETER_UNKNOWN
DEF
BYTEENA_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
INDATA_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
WRCONTROL_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
ADDRESS_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
OUTDATA_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
RDCONTROL_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
BYTEENA_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
WIDTH_BYTEENA_A
1
PARAMETER_UNKNOWN
DEF
WIDTH_BYTEENA_B
1
PARAMETER_UNKNOWN
DEF
RAM_BLOCK_TYPE
AUTO
PARAMETER_UNKNOWN
DEF
BYTE_SIZE
8
PARAMETER_UNKNOWN
DEF
READ_DURING_WRITE_MODE_MIXED_PORTS
DONT_CARE
PARAMETER_UNKNOWN
DEF
INIT_FILE
TEST0.rtl.mif
PARAMETER_UNKNOWN
USR
INIT_FILE_LAYOUT
PORT_A
PARAMETER_UNKNOWN
DEF
MAXIMUM_DEPTH
0
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_INPUT_A
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_INPUT_B
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_OUTPUT_A
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_OUTPUT_B
NORMAL
PARAMETER_UNKNOWN
DEF
DEVICE_FAMILY
Cyclone
PARAMETER_UNKNOWN
USR
CBXI_PARAMETER
altsyncram_jvi
PARAMETER_UNKNOWN
USR
}
# used_port {
address_a0
address_a1
address_a2
address_a3
address_a4
address_a5
address_a6
address_a7
clock0
q_a0
q_a1
q_a2
q_a3
q_a4
q_a5
q_a6
}
# include_file {
c:|altera|quartus41|libraries|megafunctions|stratix_ram_block.inc
1081479498
c:|altera|quartus41|libraries|megafunctions|lpm_mux.inc
1081478758
c:|altera|quartus41|libraries|megafunctions|lpm_decode.inc
1081478592
c:|altera|quartus41|libraries|megafunctions|aglobal41.inc
1088009406
c:|altera|quartus41|libraries|megafunctions|altsyncram.inc
1081477654
c:|altera|quartus41|libraries|megafunctions|a_rdenreg.inc
1081476578
c:|altera|quartus41|libraries|megafunctions|altrom.inc
1081477590
c:|altera|quartus41|libraries|megafunctions|altram.inc
1081477560
c:|altera|quartus41|libraries|megafunctions|altdpram.inc
1081477328
c:|altera|quartus41|libraries|megafunctions|altqpram.inc
1081477546
}
# end
# entity
altsyncram_jvi
# case_insensitive
# source_file
db|altsyncram_jvi.tdf
1123638284
6
# storage
db|TEST.(21).cnf
db|TEST.(21).cnf
# used_port {
address_a0
address_a1
address_a2
address_a3
address_a4
address_a5
address_a6
address_a7
clock0
q_a0
q_a1
q_a2
q_a3
q_a4
q_a5
q_a6
}
# memory_file {
TEST0.rtl.mif
0
}
# end
# complete
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