test.hif

数字示波器的FPGA实现 VHDL编写 Quartus7.1测试通过

Version 4.1 Build 181 06/29/2004 SJ Full Version
31
OFF
OFF
OFF
OFF
0
# entity
MAX114
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
MAX114.vhd
1091409480
4
# storage
db|test.(0).cnf
db|test.(0).cnf
# internal_option {
AUTO_RESOURCE_SHARING
OFF
PRESERVE_REGISTER
OFF
DUP_REG_EXTRACTION
ON
DUP_LOGIC_EXTRACTION
ON
VHDL_VERILOG_BREAK_LOOPS
OFF
}
# end
# entity
altsyncram
# case_insensitive
# source_file
c:|altera|quartus41|libraries|megafunctions|altsyncram.tdf
1088009418
6
# storage
db|test.(2).cnf
db|test.(2).cnf
# user_parameter {
BYTE_SIZE_BLOCK
8
PARAMETER_UNKNOWN
DEF
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
OPERATION_MODE
ROM
PARAMETER_UNKNOWN
USR
WIDTH_A
6
PARAMETER_UNKNOWN
USR
WIDTHAD_A
8
PARAMETER_UNKNOWN
USR
NUMWORDS_A
256
PARAMETER_UNKNOWN
USR
OUTDATA_REG_A
UNREGISTERED
PARAMETER_UNKNOWN
USR
ADDRESS_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
OUTDATA_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
WRCONTROL_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
INDATA_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
BYTEENA_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
WIDTH_B
1
PARAMETER_UNKNOWN
DEF
WIDTHAD_B
1
PARAMETER_UNKNOWN
DEF
NUMWORDS_B
1
PARAMETER_UNKNOWN
DEF
INDATA_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
WRCONTROL_WRADDRESS_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
RDCONTROL_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
ADDRESS_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
OUTDATA_REG_B
UNREGISTERED
PARAMETER_UNKNOWN
DEF
BYTEENA_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
INDATA_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
WRCONTROL_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
ADDRESS_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
OUTDATA_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
RDCONTROL_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
BYTEENA_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
WIDTH_BYTEENA_A
1
PARAMETER_UNKNOWN
DEF
WIDTH_BYTEENA_B
1
PARAMETER_UNKNOWN
DEF
RAM_BLOCK_TYPE
AUTO
PARAMETER_UNKNOWN
DEF
BYTE_SIZE
8
PARAMETER_UNKNOWN
DEF
READ_DURING_WRITE_MODE_MIXED_PORTS
DONT_CARE
PARAMETER_UNKNOWN
DEF
INIT_FILE
BUS_10.rtl.mif
PARAMETER_UNKNOWN
USR
INIT_FILE_LAYOUT
PORT_A
PARAMETER_UNKNOWN
DEF
MAXIMUM_DEPTH
0
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_INPUT_A
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_INPUT_B
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_OUTPUT_A
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_OUTPUT_B
NORMAL
PARAMETER_UNKNOWN
DEF
DEVICE_FAMILY
Cyclone
PARAMETER_UNKNOWN
USR
CBXI_PARAMETER
altsyncram_c0j
PARAMETER_UNKNOWN
USR
}
# used_port {
address_a0
address_a1
address_a2
address_a3
address_a4
address_a5
address_a6
address_a7
clock0
q_a0
q_a1
q_a2
q_a3
q_a4
q_a5
}
# include_file {
c:|altera|quartus41|libraries|megafunctions|stratix_ram_block.inc
1081479498
c:|altera|quartus41|libraries|megafunctions|lpm_mux.inc
1081478758
c:|altera|quartus41|libraries|megafunctions|lpm_decode.inc
1081478592
c:|altera|quartus41|libraries|megafunctions|aglobal41.inc
1088009406
c:|altera|quartus41|libraries|megafunctions|altsyncram.inc
1081477654
c:|altera|quartus41|libraries|megafunctions|a_rdenreg.inc
1081476578
c:|altera|quartus41|libraries|megafunctions|altrom.inc
1081477590
c:|altera|quartus41|libraries|megafunctions|altram.inc
1081477560
c:|altera|quartus41|libraries|megafunctions|altdpram.inc
1081477328
c:|altera|quartus41|libraries|megafunctions|altqpram.inc
1081477546
}
# end
# entity
generator_reg81
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
GENERATOR_REG81.vhd
1123301414
4
# storage
db|test.(5).cnf
db|test.(5).cnf
# internal_option {
AUTO_RESOURCE_SHARING
OFF
PRESERVE_REGISTER
OFF
DUP_REG_EXTRACTION
ON
DUP_LOGIC_EXTRACTION
ON
VHDL_VERILOG_BREAK_LOOPS
OFF
}
# end
# entity
generator_reg8
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
GENERATOR_REG8.vhd
1122958834
4
# storage
db|test.(6).cnf
db|test.(6).cnf
# internal_option {
AUTO_RESOURCE_SHARING
OFF
PRESERVE_REGISTER
OFF
DUP_REG_EXTRACTION
ON
DUP_LOGIC_EXTRACTION
ON
VHDL_VERILOG_BREAK_LOOPS
OFF
}
# end
# entity
SRAM_ADW
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
SRAM_ADW.vhd
1123115950
4
# storage
db|test.(7).cnf
db|test.(7).cnf
# internal_option {
AUTO_RESOURCE_SHARING
OFF
PRESERVE_REGISTER
OFF
DUP_REG_EXTRACTION
ON
DUP_LOGIC_EXTRACTION
ON
VHDL_VERILOG_BREAK_LOOPS
OFF
}
# end
# entity
GET_RDADDR
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
GET_RDADDR.VHD
1123468968
4
# storage
db|test.(4).cnf
db|test.(4).cnf
# internal_option {
AUTO_RESOURCE_SHARING
OFF
PRESERVE_REGISTER
OFF
DUP_REG_EXTRACTION
ON
DUP_LOGIC_EXTRACTION
ON
VHDL_VERILOG_BREAK_LOOPS
OFF
}
# end
# entity
AD_SRAM
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
AD_SRAM.vhd
1123474878
4
# storage
db|test.(8).cnf
db|test.(8).cnf
# internal_option {
AUTO_RESOURCE_SHARING
OFF
PRESERVE_REGISTER
OFF
DUP_REG_EXTRACTION
ON
DUP_LOGIC_EXTRACTION
ON
VHDL_VERILOG_BREAK_LOOPS
OFF
}
# end
# entity
VOLTAGE_CONV
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
VOLTAGE_CONV.vhd
1123491404
4
# storage
db|test.(9).cnf
db|test.(9).cnf
# internal_option {
AUTO_RESOURCE_SHARING
OFF
PRESERVE_REGISTER
OFF
DUP_REG_EXTRACTION
ON
DUP_LOGIC_EXTRACTION
ON
VHDL_VERILOG_BREAK_LOOPS
OFF
}
# end
# entity
CONV_SINGLE
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
CONV_SINGLE.vhd
1123475188
4
# storage
db|test.(10).cnf
db|test.(10).cnf
# internal_option {
AUTO_RESOURCE_SHARING
OFF
PRESERVE_REGISTER
OFF
DUP_REG_EXTRACTION
ON
DUP_LOGIC_EXTRACTION
ON
VHDL_VERILOG_BREAK_LOOPS
OFF
}
# end
# entity
LPM_BUSTRI
# case_insensitive
# source_file
c:|altera|quartus41|libraries|megafunctions|LPM_BUSTRI.tdf
1088009428
6
# storage
db|test.(12).cnf
db|test.(12).cnf
# user_parameter {
LPM_WIDTH
8
PARAMETER_UNKNOWN
USR
}
# used_port {
data0
data1
data2
data3
data4
data5
data6
data7
enabledt
enabletr
result0
result1
result2
result3
result4
result5
result6
result7
tridata0
tridata1
tridata2
tridata3
tridata4
tridata5
tridata6
tridata7
}
# end
# entity
dram
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
dram.vhd
1123420052
4
# storage
db|test.(13).cnf
db|test.(13).cnf
# internal_option {
AUTO_RESOURCE_SHARING
OFF
PRESERVE_REGISTER
OFF
DUP_REG_EXTRACTION
ON
DUP_LOGIC_EXTRACTION
ON
VHDL_VERILOG_BREAK_LOOPS
OFF
}
# end
# entity
altsyncram
# case_insensitive
# source_file
c:|altera|quartus41|libraries|megafunctions|altsyncram.tdf
1088009418
6
# storage
db|test.(14).cnf
db|test.(14).cnf
# user_parameter {
BYTE_SIZE_BLOCK
8
PARAMETER_UNKNOWN
DEF
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
OPERATION_MODE
DUAL_PORT
PARAMETER_UNKNOWN
USR
WIDTH_A
8
PARAMETER_DEC
USR
WIDTHAD_A
11
PARAMETER_DEC
USR
NUMWORDS_A
2000
PARAMETER_DEC
USR
OUTDATA_REG_A
UNREGISTERED
PARAMETER_UNKNOWN
DEF
ADDRESS_ACLR_A
NONE
PARAMETER_UNKNOWN
USR
OUTDATA_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
WRCONTROL_ACLR_A
NONE
PARAMETER_UNKNOWN
USR
INDATA_ACLR_A
NONE
PARAMETER_UNKNOWN
USR
BYTEENA_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
WIDTH_B
8
PARAMETER_DEC
USR
WIDTHAD_B
11
PARAMETER_DEC
USR
NUMWORDS_B
2000
PARAMETER_DEC
USR
INDATA_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
WRCONTROL_WRADDRESS_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
RDCONTROL_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
ADDRESS_REG_B
CLOCK1
PARAMETER_UNKNOWN
USR
OUTDATA_REG_B
UNREGISTERED
PARAMETER_UNKNOWN
USR
BYTEENA_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
INDATA_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
WRCONTROL_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
ADDRESS_ACLR_B
NONE
PARAMETER_UNKNOWN
USR
OUTDATA_ACLR_B
NONE
PARAMETER_UNKNOWN
USR
RDCONTROL_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
BYTEENA_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
WIDTH_BYTEENA_A
1
PARAMETER_DEC
USR
WIDTH_BYTEENA_B
1
PARAMETER_UNKNOWN
DEF
RAM_BLOCK_TYPE
M4K
PARAMETER_UNKNOWN
USR
BYTE_SIZE
8
PARAMETER_UNKNOWN
DEF
READ_DURING_WRITE_MODE_MIXED_PORTS
DONT_CARE
PARAMETER_UNKNOWN
DEF
INIT_FILE
UNUSED
PARAMETER_UNKNOWN
DEF
INIT_FILE_LAYOUT
PORT_A
PARAMETER_UNKNOWN
DEF
MAXIMUM_DEPTH
2048
PARAMETER_DEC
USR
CLOCK_ENABLE_INPUT_A
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_INPUT_B
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_OUTPUT_A
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_OUTPUT_B
NORMAL
PARAMETER_UNKNOWN
DEF
DEVICE_FAMILY
Cyclone
PARAMETER_UNKNOWN
USR
CBXI_PARAMETER
altsyncram_8r81
PARAMETER_UNKNOWN
USR
}
# used_port {
address_a0
address_a10
address_a1
address_a2
address_a3
address_a4
address_a5
address_a6
address_a7
address_a8
address_a9
address_b0
address_b10
address_b1
address_b2
address_b3
address_b4
address_b5
address_b6
address_b7
address_b8
address_b9
clock0
clock1
data_a0