cntr_eq7.tdf

数字示波器的FPGA实现 VHDL编写 Quartus7.1测试通过

--lpm_counter DEVICE_FAMILY="Cyclone" lpm_direction="UP" lpm_width=16 aclr aset clock q
--VERSION_BEGIN 4.1 cbx_cycloneii 2004:05:18:11:27:16:SJ cbx_lpm_add_sub 2004:06:23:12:24:04:SJ cbx_lpm_compare 2004:04:12:17:30:12:SJ cbx_lpm_counter 2004:04:21:01:21:20:SJ cbx_lpm_decode 2004:03:10:10:44:06:SJ cbx_mgl 2004:06:17:17:30:06:SJ cbx_stratix 2004:04:28:15:20:14:SJ cbx_stratixii 2004:05:18:11:28:28:SJ  VERSION_END


--  Copyright (C) 1988-2002 Altera Corporation
--  Any  megafunction  design,  and related netlist (encrypted  or  decrypted),
--  support information,  device programming or simulation file,  and any other
--  associated  documentation or information  provided by  Altera  or a partner
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--  to program  PLD  devices (but not masked  PLD  devices) from  Altera.   Any
--  other  use  of such  megafunction  design,  netlist,  support  information,
--  device programming or simulation file,  or any other  related documentation
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--  limited to  modification,  reverse engineering,  de-compiling, or use  with
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FUNCTION cyclone_lcell (aclr, aload, cin, clk, dataa, datab, datac, datad, ena, inverta, regcascin, sclr, sload)
WITH ( 	cin_used,	lut_mask,	operation_mode,	output_mode,	register_cascade_mode,	sum_lutc_input,	synch_mode) 
RETURNS ( combout, cout, regout);

--synthesis_resources = lut 16 
SUBDESIGN cntr_eq7
( 
	aclr	:	input;
	aset	:	input;
	clock	:	input;
	cout	:	output;
	q[15..0]	:	output;
) 
VARIABLE 
	counter_cella0 : cyclone_lcell
		WITH (
			cin_used = "false",
			lut_mask = "5599",
			operation_mode = "arithmetic",
			synch_mode = "on"
		);
	counter_cella1 : cyclone_lcell
		WITH (
			cin_used = "true",
			lut_mask = "5A90",
			operation_mode = "arithmetic",
			sum_lutc_input = "cin",
			synch_mode = "on"
		);
	counter_cella2 : cyclone_lcell
		WITH (
			cin_used = "true",
			lut_mask = "5A90",
			operation_mode = "arithmetic",
			sum_lutc_input = "cin",
			synch_mode = "on"
		);
	counter_cella3 : cyclone_lcell
		WITH (
			cin_used = "true",
			lut_mask = "5A90",
			operation_mode = "arithmetic",
			sum_lutc_input = "cin",
			synch_mode = "on"
		);
	counter_cella4 : cyclone_lcell
		WITH (
			cin_used = "true",
			lut_mask = "5A90",
			operation_mode = "arithmetic",
			sum_lutc_input = "cin",
			synch_mode = "on"
		);
	counter_cella5 : cyclone_lcell
		WITH (
			cin_used = "true",
			lut_mask = "5A90",
			operation_mode = "arithmetic",
			sum_lutc_input = "cin",
			synch_mode = "on"
		);
	counter_cella6 : cyclone_lcell
		WITH (
			cin_used = "true",
			lut_mask = "5A90",
			operation_mode = "arithmetic",
			sum_lutc_input = "cin",
			synch_mode = "on"
		);
	counter_cella7 : cyclone_lcell
		WITH (
			cin_used = "true",
			lut_mask = "5A90",
			operation_mode = "arithmetic",
			sum_lutc_input = "cin",
			synch_mode = "on"
		);
	counter_cella8 : cyclone_lcell
		WITH (
			cin_used = "true",
			lut_mask = "5A90",
			operation_mode = "arithmetic",
			sum_lutc_input = "cin",
			synch_mode = "on"
		);
	counter_cella9 : cyclone_lcell
		WITH (
			cin_used = "true",
			lut_mask = "5A90",
			operation_mode = "arithmetic",
			sum_lutc_input = "cin",
			synch_mode = "on"
		);
	counter_cella10 : cyclone_lcell
		WITH (
			cin_used = "true",
			lut_mask = "5A90",
			operation_mode = "arithmetic",
			sum_lutc_input = "cin",
			synch_mode = "on"
		);
	counter_cella11 : cyclone_lcell
		WITH (
			cin_used = "true",
			lut_mask = "5A90",
			operation_mode = "arithmetic",
			sum_lutc_input = "cin",
			synch_mode = "on"
		);
	counter_cella12 : cyclone_lcell
		WITH (
			cin_used = "true",
			lut_mask = "5A90",
			operation_mode = "arithmetic",
			sum_lutc_input = "cin",
			synch_mode = "on"
		);
	counter_cella13 : cyclone_lcell
		WITH (
			cin_used = "true",
			lut_mask = "5A90",
			operation_mode = "arithmetic",
			sum_lutc_input = "cin",
			synch_mode = "on"
		);
	counter_cella14 : cyclone_lcell
		WITH (
			cin_used = "true",
			lut_mask = "5A90",
			operation_mode = "arithmetic",
			sum_lutc_input = "cin",
			synch_mode = "on"
		);
	counter_cella15 : cyclone_lcell
		WITH (
			cin_used = "true",
			lut_mask = "5A90",
			operation_mode = "arithmetic",
			sum_lutc_input = "cin",
			synch_mode = "on"
		);
	a_data[15..0]	: WIRE;
	a_val[15..0]	: WIRE;
	aclr_actual	: WIRE;
	aload	: NODE;
	aset_node	: WIRE;
	clk_en	: NODE;
	cnt_en	: NODE;
	data[15..0]	: NODE;
	effective_clrn[15..0]	: WIRE;
	effective_prn[15..0]	: WIRE;
	latch_signal[15..0]	: WIRE;
	pre_hazard[15..0]	: WIRE;
	pre_latch_signal[15..0]	: WIRE;
	s_val[15..0]	: WIRE;
	safe_q[15..0]	: WIRE;
	sclr	: NODE;
	sload	: NODE;
	sset_node	: WIRE;
	time_to_clear	: WIRE;
	updownDir	: WIRE;

BEGIN 
	counter_cella[15..0].aclr = aclr_actual;
	counter_cella[1].cin = counter_cella[0].cout;
	counter_cella[2].cin = counter_cella[1].cout;
	counter_cella[3].cin = counter_cella[2].cout;
	counter_cella[4].cin = counter_cella[3].cout;
	counter_cella[5].cin = counter_cella[4].cout;
	counter_cella[6].cin = counter_cella[5].cout;
	counter_cella[7].cin = counter_cella[6].cout;
	counter_cella[8].cin = counter_cella[7].cout;
	counter_cella[9].cin = counter_cella[8].cout;
	counter_cella[10].cin = counter_cella[9].cout;
	counter_cella[11].cin = counter_cella[10].cout;
	counter_cella[12].cin = counter_cella[11].cout;
	counter_cella[13].cin = counter_cella[12].cout;
	counter_cella[14].cin = counter_cella[13].cout;
	counter_cella[15].cin = counter_cella[14].cout;
	counter_cella[15..0].clk = clock;
	counter_cella[15..0].dataa = counter_cella[15..0].regout;
	counter_cella[15..0].datab = (! (updownDir $ latch_signal[]));
	counter_cella[15..0].datac = ((! latch_signal[]) $ ((! sclr) & ((sset_node & s_val[]) # ((! sset_node) & data[]))));
	counter_cella[15..0].ena = (clk_en & (((cnt_en # sclr) # sset_node) # sload));
	counter_cella[15..0].sclr = B"0000000000000000";
	counter_cella[15..0].sload = ((sclr # sset_node) # sload);
	a_data[] = ((aset_node & a_val[]) # ((! aset_node) & data[]));
	a_val[] = B"1111111111111111";
	aclr_actual = ((aclr # aset_node) # aload);
	aload = GND;
	aset_node = aset;
	clk_en = VCC;
	cnt_en = VCC;
	cout = counter_cella[15].cout;
	data[] = GND;
	effective_clrn[] = (! (aclr # ((! a_data[]) & (aload # aset_node))));
	effective_prn[] = (! ((aload # aset_node) & a_data[]));
	latch_signal[] = ((! effective_clrn[]) # pre_latch_signal[]);
	pre_hazard[] = counter_cella[15..0].regout;
	pre_latch_signal[] = (effective_prn[] & latch_signal[]);
	q[] = safe_q[];
	s_val[] = B"1111111111111111";
	safe_q[] = ((((pre_hazard[] & latch_signal[]) & effective_clrn[]) # (((! latch_signal[]) & (! pre_hazard[])) & effective_clrn[])) # ((! aclr) & (! effective_prn[])));
	sclr = GND;
	sload = GND;
	sset_node = B"0";
	time_to_clear = B"0";
	updownDir = B"1";
END;
--VALID FILE