test.fit.qmsg

数字示波器的FPGA实现 VHDL编写 Quartus7.1测试通过

{ "Info" "IFSAC_FSAC_IO_STATS_BEFORE_AFTER_PLACEMENT" "before " "Info: Details of I/O bank before I/O pin placement" { { "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O banks " "Info: Statistics of I/O banks" { { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "1 does not use unused 4 18 " "Info: I/O bank number 1 does not use VREF pins and has unused VCCIO pins. 4 total pin(s) used --  18 pins available" {  } {  } 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "2 does not use unused 0 28 " "Info: I/O bank number 2 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  28 pins available" {  } {  } 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "3 does not use unused 0 24 " "Info: I/O bank number 3 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  24 pins available" {  } {  } 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "4 does not use unused 0 28 " "Info: I/O bank number 4 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  28 pins available" {  } {  } 0}  } {  } 0}  } {  } 0}
{ "Info" "IFSAC_FSAC_IO_STATS_BEFORE_AFTER_PLACEMENT" "after " "Info: Details of I/O bank after I/O pin placement" { { "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O banks " "Info: Statistics of I/O banks" { { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "1 does not use 3.30V 12 10 " "Info: I/O bank number 1 does not use VREF pins and has 3.30V VCCIO pins. 12 total pin(s) used --  10 pins available" {  } {  } 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "2 does not use 3.30V 24 4 " "Info: I/O bank number 2 does not use VREF pins and has 3.30V VCCIO pins. 24 total pin(s) used --  4 pins available" {  } {  } 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "3 does not use unused 17 7 " "Info: I/O bank number 3 does not use VREF pins and has unused VCCIO pins. 17 total pin(s) used --  7 pins available" {  } {  } 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "4 does not use unused 0 28 " "Info: I/O bank number 4 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  28 pins available" {  } {  } 0}  } {  } 0}  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Info: Fitter placement preparation operations beginning" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "0 " "Info: Fitter placement preparation operations ending: elapsed time = 0 seconds" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Info: Fitter placement operations beginning" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Info: Fitter placement was successful" {  } {  } 0}
{ "Info" "ITDB_FULL_ESTIMATED_DATA_PATH_RESULT" "5.371 ns register register " "Info: Estimated most critical path is register to register delay of 5.371 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns BUS_1:inst9\|RAMTMP7\[0\] 1 REG LAB_X24_Y4 3 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X24_Y4; Fanout = 3; REG Node = 'BUS_1:inst9\|RAMTMP7\[0\]'" {  } { { "e:/ywh/quartusii/scanwave/db/TEST_cmp.qrpt" "" "" { Report "e:/ywh/quartusii/scanwave/db/TEST_cmp.qrpt" Compiler "TEST" "UNKNOWN" "V1" "e:/ywh/quartusii/scanwave/db/TEST.quartus_db" { Floorplan "" "" "" { BUS_1:inst9|RAMTMP7[0] } "NODE_NAME" } } } { "e:/ywh/quartusii/scanwave/BUS_1.vhd" "" "" { Text "e:/ywh/quartusii/scanwave/BUS_1.vhd" 56 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.765 ns) + CELL(0.432 ns) 1.197 ns CONV_SINGLE:inst5\|LessThan~1COUT1 2 COMB LAB_X23_Y4 1 " "Info: 2: + IC(0.765 ns) + CELL(0.432 ns) = 1.197 ns; Loc. = LAB_X23_Y4; Fanout = 1; COMB Node = 'CONV_SINGLE:inst5\|LessThan~1COUT1'" {  } { { "e:/ywh/quartusii/scanwave/db/TEST_cmp.qrpt" "" "" { Report "e:/ywh/quartusii/scanwave/db/TEST_cmp.qrpt" Compiler "TEST" "UNKNOWN" "V1" "e:/ywh/quartusii/scanwave/db/TEST.quartus_db" { Floorplan "" "" "1.197 ns" { BUS_1:inst9|RAMTMP7[0] CONV_SINGLE:inst5|LessThan~1COUT1 } "NODE_NAME" } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 1.277 ns CONV_SINGLE:inst5\|LessThan~2COUT1 3 COMB LAB_X23_Y4 1 " "Info: 3: + IC(0.000 ns) + CELL(0.080 ns) = 1.277 ns; Loc. = LAB_X23_Y4; Fanout = 1; COMB Node = 'CONV_SINGLE:inst5\|LessThan~2COUT1'" {  } { { "e:/ywh/quartusii/scanwave/db/TEST_cmp.qrpt" "" "" { Report "e:/ywh/quartusii/scanwave/db/TEST_cmp.qrpt" Compiler "TEST" "UNKNOWN" "V1" "e:/ywh/quartusii/scanwave/db/TEST.quartus_db" { Floorplan "" "" "0.080 ns" { CONV_SINGLE:inst5|LessThan~1COUT1 CONV_SINGLE:inst5|LessThan~2COUT1 } "NODE_NAME" } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 1.357 ns CONV_SINGLE:inst5\|LessThan~3COUT1 4 COMB LAB_X23_Y4 1 " "Info: 4: + IC(0.000 ns) + CELL(0.080 ns) = 1.357 ns; Loc. = LAB_X23_Y4; Fanout = 1; COMB Node = 'CONV_SINGLE:inst5\|LessThan~3COUT1'" {  } { { "e:/ywh/quartusii/scanwave/db/TEST_cmp.qrpt" "" "" { Report "e:/ywh/quartusii/scanwave/db/TEST_cmp.qrpt" Compiler "TEST" "UNKNOWN" "V1" "e:/ywh/quartusii/scanwave/db/TEST.quartus_db" { Floorplan "" "" "0.080 ns" { CONV_SINGLE:inst5|LessThan~2COUT1 CONV_SINGLE:inst5|LessThan~3COUT1 } "NODE_NAME" } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 1.437 ns CONV_SINGLE:inst5\|LessThan~4COUT1 5 COMB LAB_X23_Y4 1 " "Info: 5: + IC(0.000 ns) + CELL(0.080 ns) = 1.437 ns; Loc. = LAB_X23_Y4; Fanout = 1; COMB Node = 'CONV_SINGLE:inst5\|LessThan~4COUT1'" {  } { { "e:/ywh/quartusii/scanwave/db/TEST_cmp.qrpt" "" "" { Report "e:/ywh/quartusii/scanwave/db/TEST_cmp.qrpt" Compiler "TEST" "UNKNOWN" "V1" "e:/ywh/quartusii/scanwave/db/TEST.quartus_db" { Floorplan "" "" "0.080 ns" { CONV_SINGLE:inst5|LessThan~3COUT1 CONV_SINGLE:inst5|LessThan~4COUT1 } "NODE_NAME" } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.258 ns) 1.695 ns CONV_SINGLE:inst5\|LessThan~5 6 COMB LAB_X23_Y4 1 " "Info: 6: + IC(0.000 ns) + CELL(0.258 ns) = 1.695 ns; Loc. = LAB_X23_Y4; Fanout = 1; COMB Node = 'CONV_SINGLE:inst5\|LessThan~5'" {  } { { "e:/ywh/quartusii/scanwave/db/TEST_cmp.qrpt" "" "" { Report "e:/ywh/quartusii/scanwave/db/TEST_cmp.qrpt" Compiler "TEST" "UNKNOWN" "V1" "e:/ywh/quartusii/scanwave/db/TEST.quartus_db" { Floorplan "" "" "0.258 ns" { CONV_SINGLE:inst5|LessThan~4COUT1 CONV_SINGLE:inst5|LessThan~5 } "NODE_NAME" } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.679 ns) 2.374 ns CONV_SINGLE:inst5\|LessThan~8 7 COMB LAB_X23_Y4 1 " "Info: 7: + IC(0.000 ns) + CELL(0.679 ns) = 2.374 ns; Loc. = LAB_X23_Y4; Fanout = 1; COMB Node = 'CONV_SINGLE:inst5\|LessThan~8'" {  } { { "e:/ywh/quartusii/scanwave/db/TEST_cmp.qrpt" "" "" { Report "e:/ywh/quartusii/scanwave/db/TEST_cmp.qrpt" Compiler "TEST" "UNKNOWN" "V1" "e:/ywh/quartusii/scanwave/db/TEST.quartus_db" { Floorplan "" "" "0.679 ns" { CONV_SINGLE:inst5|LessThan~5 CONV_SINGLE:inst5|LessThan~8 } "NODE_NAME" } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(-0.011 ns) + CELL(0.590 ns) 2.953 ns CONV_SINGLE:inst5\|process0~0 8 COMB LAB_X23_Y4 16 " "Info: 8: + IC(-0.011 ns) + CELL(0.590 ns) = 2.953 ns; Loc. = LAB_X23_Y4; Fanout = 16; COMB Node = 'CONV_SINGLE:inst5\|process0~0'" {  } { { "e:/ywh/quartusii/scanwave/db/TEST_cmp.qrpt" "" "" { Report "e:/ywh/quartusii/scanwave/db/TEST_cmp.qrpt" Compiler "TEST" "UNKNOWN" "V1" "e:/ywh/quartusii/scanwave/db/TEST.quartus_db" { Floorplan "" "" "0.579 ns" { CONV_SINGLE:inst5|LessThan~8 CONV_SINGLE:inst5|process0~0 } "NODE_NAME" } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.760 ns) + CELL(0.442 ns) 4.155 ns AD_SRAM:inst2\|WR~0 9 COMB LAB_X21_Y4 1 " "Info: 9: + IC(0.760 ns) + CELL(0.442 ns) = 4.155 ns; Loc. = LAB_X21_Y4; Fanout = 1; COMB Node = 'AD_SRAM:inst2\|WR~0'" {  } { { "e:/ywh/quartusii/scanwave/db/TEST_cmp.qrpt" "" "" { Report "e:/ywh/quartusii/scanwave/db/TEST_cmp.qrpt" Compiler "TEST" "UNKNOWN" "V1" "e:/ywh/quartusii/scanwave/db/TEST.quartus_db" { Floorplan "" "" "1.202 ns" { CONV_SINGLE:inst5|process0~0 AD_SRAM:inst2|WR~0 } "NODE_NAME" } } } { "E:/ywh/QUARTUSII/scanwave/AD_SRAM.vhd" "" "" { Text "E:/ywh/QUARTUSII/scanwave/AD_SRAM.vhd" 24 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.349 ns) + CELL(0.867 ns) 5.371 ns AD_SRAM:inst2\|WR 10 REG LAB_X21_Y4 16 " "Info: 10: + IC(0.349 ns) + CELL(0.867 ns) = 5.371 ns; Loc. = LAB_X21_Y4; Fanout = 16; REG Node = 'AD_SRAM:inst2\|WR'" {  } { { "e:/ywh/quartusii/scanwave/db/TEST_cmp.qrpt" "" "" { Report "e:/ywh/quartusii/scanwave/db/TEST_cmp.qrpt" Compiler "TEST" "UNKNOWN" "V1" "e:/ywh/quartusii/scanwave/db/TEST.quartus_db" { Floorplan "" "" "1.216 ns" { AD_SRAM:inst2|WR~0 AD_SRAM:inst2|WR } "NODE_NAME" } } } { "E:/ywh/QUARTUSII/scanwave/AD_SRAM.vhd" "" "" { Text "E:/ywh/QUARTUSII/scanwave/AD_SRAM.vhd" 24 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.508 ns 65.31 % " "Info: Total cell delay = 3.508 ns ( 65.31 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.863 ns 34.69 % " "Info: Total interconnect delay = 1.863 ns ( 34.69 % )" {  } {  } 0}  } { { "e:/ywh/quartusii/scanwave/db/TEST_cmp.qrpt" "" "" { Report "e:/ywh/quartusii/scanwave/db/TEST_cmp.qrpt" Compiler "TEST" "UNKNOWN" "V1" "e:/ywh/quartusii/scanwave/db/TEST.quartus_db" { Floorplan "" "" "5.371 ns" { BUS_1:inst9|RAMTMP7[0] CONV_SINGLE:inst5|LessThan~1COUT1 CONV_SINGLE:inst5|LessThan~2COUT1 CONV_SINGLE:inst5|LessThan~3COUT1 CONV_SINGLE:inst5|LessThan~4COUT1 CONV_SINGLE:inst5|LessThan~5 CONV_SINGLE:inst5|LessThan~8 CONV_SINGLE:inst5|process0~0 AD_SRAM:inst2|WR~0 AD_SRAM:inst2|WR } "NODE_NAME" } } }  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_PLACER_ESTIMATED_PERCENT_ROUTING_RESOURCE_USAGE" "5 " "Info: Estimated interconnect usage is 5% of the available device resources" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "1 " "Info: Fitter placement operations ending: elapsed time = 1 seconds" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Info: Fitter routing operations beginning" {  } {  } 0}