test.map.qmsg

来自「数字示波器的FPGA实现 VHDL编写 Quartus7.1测试通过」· QMSG 代码 · 共 42 行 · 第 1/2 页

{ "Warning" "WVRFX_VHDL_ID_IN_COMB_PROCESS_HOLDS_VALUE" "save MAX114.vhd(17) " "Warning: VHDL Process Statement warning at MAX114.vhd(17): signal or variable save may not be assigned a new value in every possible path through the Process Statement. Signal or variable save holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design." {  } { { "e:/ywh/quartusii/scanwave/MAX114.vhd" "" "" { Text "e:/ywh/quartusii/scanwave/MAX114.vhd" 17 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_ID_IN_COMB_PROCESS_HOLDS_VALUE" "q MAX114.vhd(17) " "Warning: VHDL Process Statement warning at MAX114.vhd(17): signal or variable q may not be assigned a new value in every possible path through the Process Statement. Signal or variable q holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design." {  } { { "e:/ywh/quartusii/scanwave/MAX114.vhd" "" "" { Text "e:/ywh/quartusii/scanwave/MAX114.vhd" 17 0 0 } }  } 0}
{ "Info" "ISGN_SEARCH_FILE" "BUSTRI.vhd 2 1 " "Info: Using design file BUSTRI.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 BUSTRI-SYN " "Info: Found design unit 1: BUSTRI-SYN" {  } { { "e:/ywh/quartusii/scanwave/BUSTRI.vhd" "BUSTRI-SYN" "" { Text "e:/ywh/quartusii/scanwave/BUSTRI.vhd" 57 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 BUSTRI " "Info: Found entity 1: BUSTRI" {  } { { "e:/ywh/quartusii/scanwave/BUSTRI.vhd" "BUSTRI" "" { Text "e:/ywh/quartusii/scanwave/BUSTRI.vhd" 45 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "c:/altera/quartus41/libraries/megafunctions/lpm_bustri.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file c:/altera/quartus41/libraries/megafunctions/lpm_bustri.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_bustri " "Info: Found entity 1: lpm_bustri" {  } { { "c:/altera/quartus41/libraries/megafunctions/lpm_bustri.tdf" "lpm_bustri" "" { Text "c:/altera/quartus41/libraries/megafunctions/lpm_bustri.tdf" 35 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_SEARCH_FILE" "dram.vhd 2 1 " "Info: Using design file dram.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 dram-SYN " "Info: Found design unit 1: dram-SYN" {  } { { "e:/ywh/quartusii/scanwave/dram.vhd" "dram-SYN" "" { Text "e:/ywh/quartusii/scanwave/dram.vhd" 59 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 dram " "Info: Found entity 1: dram" {  } { { "e:/ywh/quartusii/scanwave/dram.vhd" "dram" "" { Text "e:/ywh/quartusii/scanwave/dram.vhd" 45 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "c:/altera/quartus41/libraries/megafunctions/altsyncram.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file c:/altera/quartus41/libraries/megafunctions/altsyncram.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram " "Info: Found entity 1: altsyncram" {  } { { "c:/altera/quartus41/libraries/megafunctions/altsyncram.tdf" "altsyncram" "" { Text "c:/altera/quartus41/libraries/megafunctions/altsyncram.tdf" 431 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_8r81.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/altsyncram_8r81.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_8r81 " "Info: Found entity 1: altsyncram_8r81" {  } { { "e:/ywh/quartusii/scanwave/db/altsyncram_8r81.tdf" "altsyncram_8r81" "" { Text "e:/ywh/quartusii/scanwave/db/altsyncram_8r81.tdf" 31 1 0 } }  } 0}  } {  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "a generator_accb.vhd(35) " "Warning: VHDL Process Statement warning at generator_accb.vhd(35): signal a is in statement, but is not in sensitivity list" {  } { { "e:/ywh/quartusii/scanwave/generator_accb.vhd" "" "" { Text "e:/ywh/quartusii/scanwave/generator_accb.vhd" 35 0 0 } }  } 0}
{ "Info" "IOPT_MLS_IGNORED_SUMMARY" "9 " "Info: Ignored 9 buffer(s)" { { "Info" "IOPT_MLS_IGNORED_SOFT" "9 " "Info: Ignored 9 SOFT buffer(s)" {  } {  } 0}  } {  } 0}
{ "Warning" "WOPT_ROM_FUNCTIONALITY_CHANGE_ALTSYNCRAM" "BUS_1:inst9\|reduce_or~37 " "Warning: Created node BUS_1:inst9\|reduce_or~37 as a ROM by generating altsyncram megafunction to implement register logic with M512 or M4K memory block. Power-up state differs from the original design." {  } {  } 0}
{ "Info" "IOPT_INFERENCING_SUMMARY" "1 " "Info: Inferred 1 megafunctions from design logic" { { "Info" "IOPT_ALTSYNCRAM_ROM_INFERRED" "BUS_1:inst9\|reduce_or~37 256 7 " "Info: Inferred altsyncram megafunction (OPERATION_MODE=ROM, NUMWORDS_A=256, WIDTH_A=7) from the following design logic: BUS_1:inst9\|reduce_or~37" {  } {  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_jvi.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/altsyncram_jvi.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_jvi " "Info: Found entity 1: altsyncram_jvi" {  } { { "e:/ywh/quartusii/scanwave/db/altsyncram_jvi.tdf" "altsyncram_jvi" "" { Text "e:/ywh/quartusii/scanwave/db/altsyncram_jvi.tdf" 31 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISMP_SMP_MACHINE_PREPROCESS_STAT" "\|test\|MAX114:39\|CURRENT_STATE 6 0 " "Info: State machine \|test\|MAX114:39\|CURRENT_STATE contains 6 states and 0 state bits" {  } {  } 0}
{ "Info" "ISMP_SMP_MACHINE_REPORT_PROCESSOR" "Auto \|test\|MAX114:39\|CURRENT_STATE " "Info: Selected Auto state machine encoding method for state machine \|test\|MAX114:39\|CURRENT_STATE" {  } {  } 0}
{ "Info" "ISMP_SMP_MACHINE_POSTPROCESS_STAT_HEADER" "\|test\|MAX114:39\|CURRENT_STATE " "Info: Encoding result for state machine \|test\|MAX114:39\|CURRENT_STATE" { { "Info" "ISMP_SMP_MACHINE_POSTPROCESS_STAT_BITS_HEADER" "6 " "Info: Completed encoding using 6 state bits" { { "Info" "ISMP_SMP_MACHINE_POSTPROCESS_STAT_BITS" "MAX114:39\|CURRENT_STATE~15 " "Info: Encoded state bit MAX114:39\|CURRENT_STATE~15" {  } {  } 0} { "Info" "ISMP_SMP_MACHINE_POSTPROCESS_STAT_BITS" "MAX114:39\|CURRENT_STATE~14 " "Info: Encoded state bit MAX114:39\|CURRENT_STATE~14" {  } {  } 0} { "Info" "ISMP_SMP_MACHINE_POSTPROCESS_STAT_BITS" "MAX114:39\|CURRENT_STATE~13 " "Info: Encoded state bit MAX114:39\|CURRENT_STATE~13" {  } {  } 0} { "Info" "ISMP_SMP_MACHINE_POSTPROCESS_STAT_BITS" "MAX114:39\|CURRENT_STATE~12 " "Info: Encoded state bit MAX114:39\|CURRENT_STATE~12" {  } {  } 0} { "Info" "ISMP_SMP_MACHINE_POSTPROCESS_STAT_BITS" "MAX114:39\|CURRENT_STATE~11 " "Info: Encoded state bit MAX114:39\|CURRENT_STATE~11" {  } {  } 0} { "Info" "ISMP_SMP_MACHINE_POSTPROCESS_STAT_BITS" "MAX114:39\|CURRENT_STATE~10 " "Info: Encoded state bit MAX114:39\|CURRENT_STATE~10" {  } {  } 0}  } {  } 0} { "Info" "ISMP_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|test\|MAX114:39\|CURRENT_STATE.st0 000000 " "Info: State \|test\|MAX114:39\|CURRENT_STATE.st0 uses code string 000000" {  } { { "e:/ywh/quartusii/scanwave/MAX114.vhd" "" "" { Text "e:/ywh/quartusii/scanwave/MAX114.vhd" 13 -1 0 } }  } 0} { "Info" "ISMP_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|test\|MAX114:39\|CURRENT_STATE.st1 000011 " "Info: State \|test\|MAX114:39\|CURRENT_STATE.st1 uses code string 000011" {  } { { "e:/ywh/quartusii/scanwave/MAX114.vhd" "" "" { Text "e:/ywh/quartusii/scanwave/MAX114.vhd" 13 -1 0 } }  } 0} { "Info" "ISMP_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|test\|MAX114:39\|CURRENT_STATE.st2 000101 " "Info: State \|test\|MAX114:39\|CURRENT_STATE.st2 uses code string 000101" {  } { { "e:/ywh/quartusii/scanwave/MAX114.vhd" "" "" { Text "e:/ywh/quartusii/scanwave/MAX114.vhd" 13 -1 0 } }  } 0} { "Info" "ISMP_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|test\|MAX114:39\|CURRENT_STATE.st3 001001 " "Info: State \|test\|MAX114:39\|CURRENT_STATE.st3 uses code string 001001" {  } { { "e:/ywh/quartusii/scanwave/MAX114.vhd" "" "" { Text "e:/ywh/quartusii/scanwave/MAX114.vhd" 13 -1 0 } }  } 0} { "Info" "ISMP_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|test\|MAX114:39\|CURRENT_STATE.st4 010001 " "Info: State \|test\|MAX114:39\|CURRENT_STATE.st4 uses code string 010001" {  } { { "e:/ywh/quartusii/scanwave/MAX114.vhd" "" "" { Text "e:/ywh/quartusii/scanwave/MAX114.vhd" 13 -1 0 } }  } 0} { "Info" "ISMP_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|test\|MAX114:39\|CURRENT_STATE.st5 100001 " "Info: State \|test\|MAX114:39\|CURRENT_STATE.st5 uses code string 100001" {  } { { "e:/ywh/quartusii/scanwave/MAX114.vhd" "" "" { Text "e:/ywh/quartusii/scanwave/MAX114.vhd" 13 -1 0 } }  } 0}  } {  } 0}
{ "Warning" "WOPT_MLS_CONVERT_TRI_TO_OR_HDR" "" "Warning: Converted TRI buffer to OR gate or removed OPNDRN" { { "Warning" "WOPT_MLS_CONVERT_TRI_TO_OR" "BUSTRI:inst11\|lpm_bustri:lpm_bustri_component\|din\[7\] " "Warning: Converting TRI node BUSTRI:inst11\|lpm_bustri:lpm_bustri_component\|din\[7\] that feeds logic to an OR gate" {  } { { "c:/altera/quartus41/libraries/megafunctions/LPM_BUSTRI.tdf" "" "" { Text "c:/altera/quartus41/libraries/megafunctions/LPM_BUSTRI.tdf" 50 6 0 } }  } 0} { "Warning" "WOPT_MLS_CONVERT_TRI_TO_OR" "BUSTRI:inst11\|lpm_bustri:lpm_bustri_component\|din\[6\] " "Warning: Converting TRI node BUSTRI:inst11\|lpm_bustri:lpm_bustri_component\|din\[6\] that feeds logic to an OR gate" {  } { { "c:/altera/quartus41/libraries/megafunctions/LPM_BUSTRI.tdf" "" "" { Text "c:/altera/quartus41/libraries/megafunctions/LPM_BUSTRI.tdf" 50 6 0 } }  } 0} { "Warning" "WOPT_MLS_CONVERT_TRI_TO_OR" "BUSTRI:inst11\|lpm_bustri:lpm_bustri_component\|din\[5\] " "Warning: Converting TRI node BUSTRI:inst11\|lpm_bustri:lpm_bustri_component\|din\[5\] that feeds logic to an OR gate" {  } { { "c:/altera/quartus41/libraries/megafunctions/LPM_BUSTRI.tdf" "" "" { Text "c:/altera/quartus41/libraries/megafunctions/LPM_BUSTRI.tdf" 50 6 0 } }  } 0} { "Warning" "WOPT_MLS_CONVERT_TRI_TO_OR" "BUSTRI:inst11\|lpm_bustri:lpm_bustri_component\|din\[4\] " "Warning: Converting TRI node BUSTRI:inst11\|lpm_bustri:lpm_bustri_component\|din\[4\] that feeds logic to an OR gate" {  } { { "c:/altera/quartus41/libraries/megafunctions/LPM_BUSTRI.tdf" "" "" { Text "c:/altera/quartus41/libraries/megafunctions/LPM_BUSTRI.tdf" 50 6 0 } }  } 0} { "Warning" "WOPT_MLS_CONVERT_TRI_TO_OR" "BUSTRI:inst11\|lpm_bustri:lpm_bustri_component\|din\[3\] " "Warning: Converting TRI node BUSTRI:inst11\|lpm_bustri:lpm_bustri_component\|din\[3\] that feeds logic to an OR gate" {  } { { "c:/altera/quartus41/libraries/megafunctions/LPM_BUSTRI.tdf" "" "" { Text "c:/altera/quartus41/libraries/megafunctions/LPM_BUSTRI.tdf" 50 6 0 } }  } 0} { "Warning" "WOPT_MLS_CONVERT_TRI_TO_OR" "BUSTRI:inst11\|lpm_bustri:lpm_bustri_component\|din\[2\] " "Warning: Converting TRI node BUSTRI:inst11\|lpm_bustri:lpm_bustri_component\|din\[2\] that feeds logic to an OR gate" {  } { { "c:/altera/quartus41/libraries/megafunctions/LPM_BUSTRI.tdf" "" "" { Text "c:/altera/quartus41/libraries/megafunctions/LPM_BUSTRI.tdf" 50 6 0 } }  } 0} { "Warning" "WOPT_MLS_CONVERT_TRI_TO_OR" "BUSTRI:inst11\|lpm_bustri:lpm_bustri_component\|din\[1\] " "Warning: Converting TRI node BUSTRI:inst11\|lpm_bustri:lpm_bustri_component\|din\[1\] that feeds logic to an OR gate" {  } { { "c:/altera/quartus41/libraries/megafunctions/LPM_BUSTRI.tdf" "" "" { Text "c:/altera/quartus41/libraries/megafunctions/LPM_BUSTRI.tdf" 50 6 0 } }  } 0} { "Warning" "WOPT_MLS_CONVERT_TRI_TO_OR" "BUSTRI:inst11\|lpm_bustri:lpm_bustri_component\|din\[0\] " "Warning: Converting TRI node BUSTRI:inst11\|lpm_bustri:lpm_bustri_component\|din\[0\] that feeds logic to an OR gate" {  } { { "c:/altera/quartus41/libraries/megafunctions/LPM_BUSTRI.tdf" "" "" { Text "c:/altera/quartus41/libraries/megafunctions/LPM_BUSTRI.tdf" 50 6 0 } }  } 0}  } {  } 0}
{ "Warning" "WOPT_MLS_STUCK_PIN_HDR" "" "Warning: Output pins are stuck at VCC or GND" { { "Warning" "WOPT_MLS_STUCK_PIN" "XFER GND " "Warning: Pin XFER stuck at GND" {  } { { "e:/ywh/quartusii/scanwave/test.bdf" "" "" { Schematic "e:/ywh/quartusii/scanwave/test.bdf" { { 688 1000 1176 704 "XFER" "" } } } }  } 0} { "Warning" "WOPT_MLS_STUCK_PIN" "A1 GND " "Warning: Pin A1 stuck at GND" {  } { { "e:/ywh/quartusii/scanwave/test.bdf" "" "" { Schematic "e:/ywh/quartusii/scanwave/test.bdf" { { 624 1000 1176 640 "A1" "" } } } }  } 0} { "Warning" "WOPT_MLS_STUCK_PIN" "CSDA2 GND " "Warning: Pin CSDA2 stuck at GND" {  } { { "e:/ywh/quartusii/scanwave/test.bdf" "" "" { Schematic "e:/ywh/quartusii/scanwave/test.bdf" { { 672 1000 1176 688 "CSDA2" "" } } } }  } 0} { "Warning" "WOPT_MLS_STUCK_PIN" "CSDA1 GND " "Warning: Pin CSDA1 stuck at GND" {  } { { "e:/ywh/quartusii/scanwave/test.bdf" "" "" { Schematic "e:/ywh/quartusii/scanwave/test.bdf" { { 656 1000 1176 672 "CSDA1" "" } } } }  } 0} { "Warning" "WOPT_MLS_STUCK_PIN" "WRDA GND " "Warning: Pin WRDA stuck at GND" {  } { { "e:/ywh/quartusii/scanwave/test.bdf" "" "" { Schematic "e:/ywh/quartusii/scanwave/test.bdf" { { 640 1000 1176 656 "WRDA" "" } } } }  } 0} { "Warning" "WOPT_MLS_STUCK_PIN" "A0 GND " "Warning: Pin A0 stuck at GND" {  } { { "e:/ywh/quartusii/scanwave/test.bdf" "" "" { Schematic "e:/ywh/quartusii/scanwave/test.bdf" { { 608 1000 1176 624 "A0" "" } } } }  } 0}  } {  } 0}
{ "Warning" "WSCL_SCL_UNNECESSARY_INPUT_PIN_HDR" "5 " "Warning: Design contains 5 input pin(s) that do not drive logic" { { "Warning" "WSCL_SCL_UNNECESSARY_INPUT_PIN" "P2\[4\] " "Warning: No output dependent on input pin P2\[4\]" {  } { { "e:/ywh/quartusii/scanwave/test.bdf" "" "" { Schematic "e:/ywh/quartusii/scanwave/test.bdf" { { 840 32 200 856 "P2\[4..0\]" "" } } } }  } 0} { "Warning" "WSCL_SCL_UNNECESSARY_INPUT_PIN" "P2\[3\] " "Warning: No output dependent on input pin P2\[3\]" {  } { { "e:/ywh/quartusii/scanwave/test.bdf" "" "" { Schematic "e:/ywh/quartusii/scanwave/test.bdf" { { 840 32 200 856 "P2\[4..0\]" "" } } } }  } 0} { "Warning" "WSCL_SCL_UNNECESSARY_INPUT_PIN" "P2\[2\] " "Warning: No output dependent on input pin P2\[2\]" {  } { { "e:/ywh/quartusii/scanwave/test.bdf" "" "" { Schematic "e:/ywh/quartusii/scanwave/test.bdf" { { 840 32 200 856 "P2\[4..0\]" "" } } } }  } 0} { "Warning" "WSCL_SCL_UNNECESSARY_INPUT_PIN" "P2\[1\] " "Warning: No output dependent on input pin P2\[1\]" {  } { { "e:/ywh/quartusii/scanwave/test.bdf" "" "" { Schematic "e:/ywh/quartusii/scanwave/test.bdf" { { 840 32 200 856 "P2\[4..0\]" "" } } } }  } 0} { "Warning" "WSCL_SCL_UNNECESSARY_INPUT_PIN" "P2\[0\] " "Warning: No output dependent on input pin P2\[0\]" {  } { { "e:/ywh/quartusii/scanwave/test.bdf" "" "" { Schematic "e:/ywh/quartusii/scanwave/test.bdf" { { 840 32 200 856 "P2\[4..0\]" "" } } } }  } 0}  } {  } 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "356 " "Info: Implemented 356 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "19 " "Info: Implemented 19 input pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_OPINS" "24 " "Info: Implemented 24 output pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_BIDIRS" "8 " "Info: Implemented 8 bidirectional pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_LCELLS" "290 " "Info: Implemented 290 logic cells" {  } {  } 0} { "Info" "ISCL_SCL_TM_RAMS" "15 " "Info: Implemented 15 RAM segments" {  } {  } 0}  } {  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 29 s " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 29 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Wed Aug 10 09:44:47 2005 " "Info: Processing ended: Wed Aug 10 09:44:47 2005" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:09 " "Info: Elapsed time: 00:00:09" {  } {  } 0}  } {  } 0}