test.map.qmsg

数字示波器的FPGA实现 VHDL编写 Quartus7.1测试通过

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 4.1 Build 181 06/29/2004 SJ Full Version " "Info: Version 4.1 Build 181 06/29/2004 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Wed Aug 10 09:44:38 2005 " "Info: Processing started: Wed Aug 10 09:44:38 2005" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --import_settings_files=on --export_settings_files=off TEST -c TEST " "Info: Command: quartus_map --import_settings_files=on --export_settings_files=off TEST -c TEST" {  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "AD_SRAM.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file AD_SRAM.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 AD_SRAM-ART " "Info: Found design unit 1: AD_SRAM-ART" {  } { { "e:/ywh/quartusii/scanwave/AD_SRAM.vhd" "AD_SRAM-ART" "" { Text "e:/ywh/quartusii/scanwave/AD_SRAM.vhd" 16 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 AD_SRAM " "Info: Found entity 1: AD_SRAM" {  } { { "e:/ywh/quartusii/scanwave/AD_SRAM.vhd" "AD_SRAM" "" { Text "e:/ywh/quartusii/scanwave/AD_SRAM.vhd" 6 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "BUS_1.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file BUS_1.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 BUS_1-ART " "Info: Found design unit 1: BUS_1-ART" {  } { { "e:/ywh/quartusii/scanwave/BUS_1.vhd" "BUS_1-ART" "" { Text "e:/ywh/quartusii/scanwave/BUS_1.vhd" 16 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 BUS_1 " "Info: Found entity 1: BUS_1" {  } { { "e:/ywh/quartusii/scanwave/BUS_1.vhd" "BUS_1" "" { Text "e:/ywh/quartusii/scanwave/BUS_1.vhd" 5 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "CONV_SINGLE.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file CONV_SINGLE.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 CONV_SINGLE-ART " "Info: Found design unit 1: CONV_SINGLE-ART" {  } { { "e:/ywh/quartusii/scanwave/CONV_SINGLE.vhd" "CONV_SINGLE-ART" "" { Text "e:/ywh/quartusii/scanwave/CONV_SINGLE.vhd" 13 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 CONV_SINGLE " "Info: Found entity 1: CONV_SINGLE" {  } { { "e:/ywh/quartusii/scanwave/CONV_SINGLE.vhd" "CONV_SINGLE" "" { Text "e:/ywh/quartusii/scanwave/CONV_SINGLE.vhd" 4 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "fredevider8.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file fredevider8.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 FREDEVIDER8-ART " "Info: Found design unit 1: FREDEVIDER8-ART" {  } { { "e:/ywh/quartusii/scanwave/fredevider8.vhd" "FREDEVIDER8-ART" "" { Text "e:/ywh/quartusii/scanwave/fredevider8.vhd" 10 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 FREDEVIDER8 " "Info: Found entity 1: FREDEVIDER8" {  } { { "e:/ywh/quartusii/scanwave/fredevider8.vhd" "FREDEVIDER8" "" { Text "e:/ywh/quartusii/scanwave/fredevider8.vhd" 4 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "generator_accb.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file generator_accb.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 generator_accB-acc_arch " "Info: Found design unit 1: generator_accB-acc_arch" {  } { { "e:/ywh/quartusii/scanwave/generator_accb.vhd" "generator_accB-acc_arch" "" { Text "e:/ywh/quartusii/scanwave/generator_accb.vhd" 29 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 generator_accB " "Info: Found entity 1: generator_accB" {  } { { "e:/ywh/quartusii/scanwave/generator_accb.vhd" "generator_accB" "" { Text "e:/ywh/quartusii/scanwave/generator_accb.vhd" 17 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "GENERATOR_ADD.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file GENERATOR_ADD.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 generator_add-add_anGen_arch " "Info: Found design unit 1: generator_add-add_anGen_arch" {  } { { "e:/ywh/quartusii/scanwave/GENERATOR_ADD.vhd" "generator_add-add_anGen_arch" "" { Text "e:/ywh/quartusii/scanwave/GENERATOR_ADD.vhd" 24 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 generator_add " "Info: Found entity 1: generator_add" {  } { { "e:/ywh/quartusii/scanwave/GENERATOR_ADD.vhd" "generator_add" "" { Text "e:/ywh/quartusii/scanwave/GENERATOR_ADD.vhd" 13 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "generator_reg8.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file generator_reg8.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 generator_reg8-reg_arch8 " "Info: Found design unit 1: generator_reg8-reg_arch8" {  } { { "e:/ywh/quartusii/scanwave/generator_reg8.vhd" "generator_reg8-reg_arch8" "" { Text "e:/ywh/quartusii/scanwave/generator_reg8.vhd" 25 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 generator_reg8 " "Info: Found entity 1: generator_reg8" {  } { { "e:/ywh/quartusii/scanwave/generator_reg8.vhd" "generator_reg8" "" { Text "e:/ywh/quartusii/scanwave/generator_reg8.vhd" 15 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "generator_reg81.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file generator_reg81.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 generator_reg81-reg_arch8 " "Info: Found design unit 1: generator_reg81-reg_arch8" {  } { { "e:/ywh/quartusii/scanwave/generator_reg81.vhd" "generator_reg81-reg_arch8" "" { Text "e:/ywh/quartusii/scanwave/generator_reg81.vhd" 26 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 generator_reg81 " "Info: Found entity 1: generator_reg81" {  } { { "e:/ywh/quartusii/scanwave/generator_reg81.vhd" "generator_reg81" "" { Text "e:/ywh/quartusii/scanwave/generator_reg81.vhd" 15 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "GET_RDADDR.VHD 2 1 " "Info: Found 2 design units, including 1 entities, in source file GET_RDADDR.VHD" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 GET_RDADDR-ART " "Info: Found design unit 1: GET_RDADDR-ART" {  } { { "e:/ywh/quartusii/scanwave/GET_RDADDR.VHD" "GET_RDADDR-ART" "" { Text "e:/ywh/quartusii/scanwave/GET_RDADDR.VHD" 15 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 GET_RDADDR " "Info: Found entity 1: GET_RDADDR" {  } { { "e:/ywh/quartusii/scanwave/GET_RDADDR.VHD" "GET_RDADDR" "" { Text "e:/ywh/quartusii/scanwave/GET_RDADDR.VHD" 7 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "max114.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file max114.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 MAX114-BEHAV " "Info: Found design unit 1: MAX114-BEHAV" {  } { { "e:/ywh/quartusii/scanwave/max114.vhd" "MAX114-BEHAV" "" { Text "e:/ywh/quartusii/scanwave/max114.vhd" 11 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 MAX114 " "Info: Found entity 1: MAX114" {  } { { "e:/ywh/quartusii/scanwave/max114.vhd" "MAX114" "" { Text "e:/ywh/quartusii/scanwave/max114.vhd" 3 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "test_AD.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file test_AD.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 test_AD " "Info: Found entity 1: test_AD" {  } { { "e:/ywh/quartusii/scanwave/test_AD.bdf" "test_AD" "" { Schematic "e:/ywh/quartusii/scanwave/test_AD.bdf" { } } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "test_SAVE1.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file test_SAVE1.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 test_SAVE1 " "Info: Found entity 1: test_SAVE1" {  } { { "e:/ywh/quartusii/scanwave/test_SAVE1.bdf" "test_SAVE1" "" { Schematic "e:/ywh/quartusii/scanwave/test_SAVE1.bdf" { } } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "VOLTAGE_CONV.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file VOLTAGE_CONV.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 VOLTAGE_CONV-ART " "Info: Found design unit 1: VOLTAGE_CONV-ART" {  } { { "e:/ywh/quartusii/scanwave/VOLTAGE_CONV.vhd" "VOLTAGE_CONV-ART" "" { Text "e:/ywh/quartusii/scanwave/VOLTAGE_CONV.vhd" 28 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 VOLTAGE_CONV " "Info: Found entity 1: VOLTAGE_CONV" {  } { { "e:/ywh/quartusii/scanwave/VOLTAGE_CONV.vhd" "VOLTAGE_CONV" "" { Text "e:/ywh/quartusii/scanwave/VOLTAGE_CONV.vhd" 17 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "test.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file test.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 test " "Info: Found entity 1: test" {  } { { "e:/ywh/quartusii/scanwave/test.bdf" "test" "" { Schematic "e:/ywh/quartusii/scanwave/test.bdf" { } } }  } 0}  } {  } 0}
{ "Warning" "WVRFX_VHDL_WARNING_INITIAL_VALUE_FOR_SIGNAL_IS_IGNORED" "current_state MAX114.vhd(13) " "Warning: VHDL Signal Declaration warning at MAX114.vhd(13): ignored default value for signal current_state" {  } { { "e:/ywh/quartusii/scanwave/MAX114.vhd" "" "" { Text "e:/ywh/quartusii/scanwave/MAX114.vhd" 13 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_WARNING_INITIAL_VALUE_FOR_SIGNAL_IS_IGNORED" "next_state MAX114.vhd(13) " "Warning: VHDL Signal Declaration warning at MAX114.vhd(13): ignored default value for signal next_state" {  } { { "e:/ywh/quartusii/scanwave/MAX114.vhd" "" "" { Text "e:/ywh/quartusii/scanwave/MAX114.vhd" 13 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "adin MAX114.vhd(34) " "Warning: VHDL Process Statement warning at MAX114.vhd(34): signal adin is in statement, but is not in sensitivity list" {  } { { "e:/ywh/quartusii/scanwave/MAX114.vhd" "" "" { Text "e:/ywh/quartusii/scanwave/MAX114.vhd" 34 0 0 } }  } 0}
{ "Info" "IVRFX_VHDL_CASE_STATEMENT_OTHERS_CLAUSE_NEVER_SELECTED" "MAX114.vhd(36) " "Info: VHDL Case Statement information at MAX114.vhd(36): OTHERS choice is never selected" {  } { { "e:/ywh/quartusii/scanwave/MAX114.vhd" "" "" { Text "e:/ywh/quartusii/scanwave/MAX114.vhd" 36 0 0 } }  } 0}