ad_sram.vhd

来自「数字示波器的FPGA实现 VHDL编写 Quartus7.1测试通过」· VHDL 代码 · 共 56 行

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;

ENTITY AD_SRAM IS
PORT(
      CLK,EN,SAVE,lock: IN STD_LOGIC;
      AIN: IN STD_LOGIC_VECTOR(7 DOWNTO 0);
      ADEN : OUT STD_LOGIC;
      DATASOUT: OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
      ADDOUT: OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
      WRS1: OUT STD_LOGIC
);
END ;

ARCHITECTURE ART OF AD_SRAM IS
begin
	process(clk, EN,lock)
    VARIABLE WR: STD_LOGIC;
	variable data : std_logic_vector (7 downto 0);
	variable cnt : integer range 0 to 4 ;
	variable cnt2 : integer range 0 to 2048 ;
	begin
	    IF EN='0' THEN 
	        CNT2:=0;
	        CNT:=0;
		ELSIF(clk 'event and clk = '1') then 
			case cnt is
				when 0 => 
                        IF SAVE='0' THEN
                        CNT:=4;
                        END IF;
				when 1 =>
					DATA:=AIN;
				when 3 =>
                    IF CNT2=2048 THEN
                        IF lock='1' THEN
                            CNT:=0;
                        ELSE CNT2:=0;
                        END IF;
                    ELSE CNT2:=CNT2+1;
                    END IF;
				when others =>
					NULL;
			end case;
			cnt := cnt + 1;
		end if; 
	ADEN<=EN;
    WRS1<='1';           
    ADDOUT<=CONV_STD_LOGIC_VECTOR(CNT2,11);
    DATASOUT<=DATA;
END PROCESS;
END ART;