mux2_3.vhd.bak

来自「数字示波器的FPGA实现 VHDL编写 Quartus7.1测试通过」· BAK 代码 · 共 18 行

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY MUX2_3 IS
PORT(
     X1,X2,X3:IN STD_LOGIC_VECTOR(7 DOWNTO 0);
	 SEL_AB:IN STD_LOGIC_VECTOR(1 DOWNTO 0);
	 Q: OUT STD_LOGIC_VECTOR(7 DOWNTO 0));
END MUX2_3;
ARCHITECTURE ART OF MUX2_3 IS
BEGIN
       WITH SEL_AB SELECT
       Q<=X1 WHEN "10" ,
	      X2 WHEN "01" ,
	      X3 WHEN "11" ;
	     "00000000" WHEN OTHERS;
END ART;