bus_1.vhd

数字示波器的FPGA实现 VHDL编写 Quartus7.1测试通过

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY BUS_1 IS
PORT(P0I: IN STD_LOGIC_VECTOR(7 DOWNTO 0);
     P0T: OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
     ALE,RD,WR,CLK: IN STD_LOGIC;
     GX,CLR,SINGLE,LOCKS: OUT STD_LOGIC;
     TRIGV: OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
     POSX: OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
     FDATA: OUT STD_LOGIC_VECTOR(21 DOWNTO 0);
     POSY_A: OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
     POSY_B: OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
     SEL_AB:OUT STD_LOGIC_VECTOR(1 DOWNTO 0):="10";
     FREQ : OUT STD_LOGIC;
     P2: IN STD_LOGIC_VECTOR(4 DOWNTO 0);
     CS: IN STD_LOGIC;
     QH,QL,AMPL: IN STD_LOGIC_VECTOR (7 DOWNTO 0));
END BUS_1;
ARCHITECTURE ART OF BUS_1 IS

  SIGNAL RAMTMP0,RAMTMP1: STD_LOGIC_VECTOR(7 DOWNTO 0);
  SIGNAL RAMTMP2,RAMTMP3: STD_LOGIC_VECTOR(7 DOWNTO 0);
  SIGNAL RAMTMP4,RAMTMP5: STD_LOGIC_VECTOR(7 DOWNTO 0);
  SIGNAL RAMTMP6,RAMTMP7: STD_LOGIC_VECTOR(7 DOWNTO 0);
  SIGNAL RAMTMP8,RAMTMP9: STD_LOGIC_VECTOR(7 DOWNTO 0);
  SIGNAL RAMTMP10,RAMTMP11,RAMTMP: STD_LOGIC_VECTOR(7 DOWNTO 0);
  SIGNAL TMP: STD_LOGIC;
  SIGNAL LATCH_ADDRES: STD_LOGIC_VECTOR(7 DOWNTO 0);
  BEGIN

  PROCESS(ALE)                    
  BEGIN
  IF ALE'EVENT AND ALE='0' THEN
      LATCH_ADDRES<=P0I;
  END IF;
  END PROCESS;

  PROCESS(CLK,RD,CS)
    VARIABLE P0_OUT: STD_LOGIC_VECTOR(7 DOWNTO 0);
  BEGIN
  IF (CLK 'EVENT AND CLK='1') THEN
  IF( RD='0')AND (CS='0') THEN
      IF LATCH_ADDRES="11110000" THEN
          GX<='1';
          P0_OUT:=QL;
      ELSIF LATCH_ADDRES="11110001" THEN
          GX<='1';
          P0_OUT:=QH;
      ELSIF LATCH_ADDRES="11110010" THEN
          GX<='1';
          P0_OUT:=AMPL;
      ELSE GX<='0';
      END IF;
  ELSE GX<='0';
  END IF;
  END IF;
  P0T<=P0_OUT;
  END PROCESS;
  
  PROCESS(CLK,WR,CS,LATCH_ADDRES)
  BEGIN
  IF (CLK 'EVENT AND CLK='0') THEN
    IF ( WR='0')AND (CS='0') THEN
      CASE LATCH_ADDRES IS
      WHEN "11110011" =>    --AB路选通
          RAMTMP0<=P0I;
          TMP<='0';
      WHEN "11110100" =>    --测频启动
          RAMTMP1<=P0I;
          TMP<='0';
      WHEN "11110101" =>    --A路Y方向移动
          RAMTMP2<=P0I;
          TMP<='0';
      WHEN "11110110" =>    --测频低八位
          RAMTMP3<=P0I;
          TMP<='0';
      WHEN "11110111" =>    --测频高八位
          RAMTMP4<=P0I;
          TMP<='0';
      WHEN "11111000" =>    --B路Y方向移动
          RAMTMP5<=P0I;
          TMP<='0';
      WHEN "11111001" =>    --触发/连续切换
          RAMTMP6<=P0I;
          TMP<='0';
      WHEN "11111010" =>    --触发电平值
          RAMTMP7<=P0I;
          TMP<='0';
      WHEN "11111011" =>    --锁存
          RAMTMP8<=P0I;
          TMP<='0';
      WHEN "11111100" =>    --X方向调频高6位
          RAMTMP9<=P0I;
          TMP<='0';
      WHEN "11111101" =>    --X方向调频低8位
          RAMTMP10<=P0I;
          TMP<='0';
      WHEN "11111110" =>    --X方向移动
          RAMTMP11<=P0I;
          TMP<='0';
      WHEN "11111111" =>    --RESET
          RAMTMP0<="00000000";
          RAMTMP1<="00000000";
          RAMTMP2<="00000000";
          RAMTMP3<="00000000";
          RAMTMP4<="00000000";
          RAMTMP5<="00000000";
          RAMTMP6<="00000000";
          RAMTMP7<="00000000";
          RAMTMP8<="00000000";
          RAMTMP9<="00000000";
          RAMTMP10<="00000000";
          RAMTMP11<="00000000";
          TMP<='1';
      WHEN OTHERS =>
          RAMTMP<=P0I;
      END CASE;
    END IF;
  END IF;
  END PROCESS;
  SEL_AB<=RAMTMP0(1 DOWNTO 0);
  --SEL_AB<="01";
  FREQ<=RAMTMP1(0);
  POSY_A<=RAMTMP2;
  POSY_B<=RAMTMP5;
  SINGLE<=RAMTMP6(0);
  TRIGV<=RAMTMP7;
  LOCKS<=RAMTMP8(0);
  FDATA<="000000" & RAMTMP9 & RAMTMP10;
  POSX<=RAMTMP11&"000";
  CLR<=TMP;
  END ART;