scanwave.tan.rpt

数字示波器的FPGA实现 VHDL编写 Quartus7.1测试通过

; Type                         ; Slack                                    ; Required Time ; Actual Time                                    ; From                         ; To                                                                                                       ; From Clock ; To Clock ; Failed Paths ;
+------------------------------+------------------------------------------+---------------+------------------------------------------------+------------------------------+----------------------------------------------------------------------------------------------------------+------------+----------+--------------+
; Worst-case tsu               ; N/A                                      ; None          ; 11.499 ns                                      ; WR                           ; BUS_1:inst5|RAMTMP5[4]                                                                                   ; --         ; CLK      ; 0            ;
; Worst-case tco               ; N/A                                      ; None          ; 17.376 ns                                      ; generator_accB:inst4|TEMP    ; DAYOUT[1]                                                                                                ; CLK        ; --       ; 0            ;
; Worst-case th                ; N/A                                      ; None          ; -0.900 ns                                      ; P0[7]                        ; BUS_1:inst5|LATCH_ADDRES[7]                                                                              ; --         ; ALE      ; 0            ;
; Worst-case Minimum tco       ; N/A                                      ; None          ; 6.795 ns                                       ; BUS_1:inst5|P0_OUT[7]        ; P0[7]                                                                                                    ; CLK        ; --       ; 0            ;
; Clock Setup: 'CLK'           ; N/A                                      ; None          ; 56.09 MHz ( period = 17.828 ns )               ; GET_RDADDR:inst10|COUNTER[7] ; dram:inst|altsyncram:altsyncram_component|altsyncram_fbg1:auto_generated|ram_block1a5~portb_address_reg7 ; CLK        ; CLK      ; 0            ;
; Clock Setup: 'CLK2'          ; N/A                                      ; None          ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; FREQ_COUNT:inst6|COUNT2[4]   ; FREQ_COUNT:inst6|COUNT2[13]                                                                              ; CLK2       ; CLK2     ; 0            ;
; Clock Hold: 'CLK'            ; Not operational: Clock Skew > Data Delay ; None          ; N/A                                            ; BUS_1:inst5|RAMTMP5[7]       ; VOLTAGE_CONV:inst17|TEMP[7]                                                                              ; CLK        ; CLK      ; 521          ;
; Total number of failed paths ;                                          ;               ;                                                ;                              ;                                                                                                          ;            ;          ; 521          ;
+------------------------------+------------------------------------------+---------------+------------------------------------------------+------------------------------+----------------------------------------------------------------------------------------------------------+------------+----------+--------------+


+------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings                                                                             ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Option                                                ; Setting            ; From ; To ; Entity Name ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Device Name                                           ; EP1C3T144C8        ;      ;    ;             ;
; Timing Models                                         ; Final              ;      ;    ;             ;
; Default hold multicycle                               ; Same as Multicycle ;      ;    ;             ;
; Cut paths between unrelated clock domains             ; On                 ;      ;    ;             ;
; Cut off read during write signal paths                ; On                 ;      ;    ;             ;
; Cut off feedback from I/O pins                        ; On                 ;      ;    ;             ;
; Report Combined Fast/Slow Timing                      ; Off                ;      ;    ;             ;
; Ignore Clock Settings                                 ; Off                ;      ;    ;             ;
; Analyze latches as synchronous elements               ; Off                ;      ;    ;             ;
; Enable Recovery/Removal analysis                      ; Off                ;      ;    ;             ;
; Enable Clock Latency                                  ; Off                ;      ;    ;             ;
; Number of source nodes to report per destination node ; 10                 ;      ;    ;             ;
; Number of destination nodes to report                 ; 10                 ;      ;    ;             ;
; Number of paths to report                             ; 200                ;      ;    ;             ;
; Report Minimum Timing Checks                          ; On                 ;      ;    ;             ;
; Use Fast Timing Models                                ; Off                ;      ;    ;             ;
; Report IO Paths Separately                            ; Off                ;      ;    ;             ;
+-------------------------------------------------------+--------------------+------+----+-------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Settings Summary                                                                                                                                                             ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; Clock Node Name ; Clock Setting Name ; Type     ; Fmax Requirement ; Early Latency ; Late Latency ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset ; Phase offset ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; CLK             ;                    ; User Pin ; None             ; 0.000 ns      ; 0.000 ns     ; --       ; N/A                   ; N/A                 ; N/A    ;              ;
; ALE             ;                    ; User Pin ; None             ; 0.000 ns      ; 0.000 ns     ; --       ; N/A                   ; N/A                 ; N/A    ;              ;