test_ad.qsf

数字示波器的FPGA实现 VHDL编写 Quartus7.1测试通过

# Copyright (C) 1991-2004 Altera Corporation
# Any  megafunction  design,  and related netlist (encrypted  or  decrypted),
# support information,  device programming or simulation file,  and any other
# associated  documentation or information  provided by  Altera  or a partner
# under  Altera's   Megafunction   Partnership   Program  may  be  used  only
# to program  PLD  devices (but not masked  PLD  devices) from  Altera.   Any
# other  use  of such  megafunction  design,  netlist,  support  information,
# device programming or simulation file,  or any other  related documentation
# or information  is prohibited  for  any  other purpose,  including, but not
# limited to  modification,  reverse engineering,  de-compiling, or use  with
# any other  silicon devices,  unless such use is  explicitly  licensed under
# a separate agreement with  Altera  or a megafunction partner.  Title to the
# intellectual property,  including patents,  copyrights,  trademarks,  trade
# secrets,  or maskworks,  embodied in any such megafunction design, netlist,
# support  information,  device programming or simulation file,  or any other
# related documentation or information provided by  Altera  or a megafunction
# partner, remains with Altera, the megafunction partner, or their respective
# licensors. No other licenses, including any licenses needed under any third
# party's intellectual property, are provided herein.


# The default values for assignments are stored in the file
#		test_ad_assignment_defaults.qdf
# If this file doesn't exist, and for assignments not listed, see file
#		assignment_defaults.qdf

# Altera recommends that you do not modify this file. This
# file is updated automatically by the Quartus II software
# and any changes you make may be lost or overwritten.


# Project-Wide Assignments
# ========================
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 4.1
set_global_assignment -name PROJECT_CREATION_TIME_DATE "20:27:22  AUGUST 07, 2005"
set_global_assignment -name LAST_QUARTUS_VERSION 4.1
set_global_assignment -name BDF_FILE test_AD.bdf

# Pin & Location Assignments
# ==========================
set_location_assignment PIN_51 -to CSDA2
set_location_assignment PIN_51 -to CSDA\[2\]
set_location_assignment PIN_52 -to DAXOUT7
set_location_assignment PIN_52 -to DAXOUT\[7\]
set_location_assignment PIN_53 -to DAXOUT6
set_location_assignment PIN_53 -to DAXOUT\[6\]
set_location_assignment PIN_54 -to DAXOUT5
set_location_assignment PIN_54 -to DAXOUT\[5\]
set_location_assignment PIN_58 -to DAXOUT4
set_location_assignment PIN_58 -to DAXOUT\[4\]
set_location_assignment PIN_59 -to DAXOUT3
set_location_assignment PIN_59 -to DAXOUT\[3\]
set_location_assignment PIN_60 -to DAXOUT2
set_location_assignment PIN_60 -to DAXOUT\[2\]
set_location_assignment PIN_61 -to DAXOUT1
set_location_assignment PIN_61 -to DAXOUT\[1\]
set_location_assignment PIN_62 -to DAXOUT0
set_location_assignment PIN_62 -to DAXOUT\[0\]
set_location_assignment PIN_50 -to XFER
set_location_assignment PIN_24 -to CSDA1
set_location_assignment PIN_24 -to CSDA\[1\]
set_location_assignment PIN_25 -to WRDA
set_location_assignment PIN_27 -to DAOUT7
set_location_assignment PIN_27 -to DAOUT\[7\]
set_location_assignment PIN_28 -to DAOUT6
set_location_assignment PIN_28 -to DAOUT\[6\]
set_location_assignment PIN_29 -to DAOUT5
set_location_assignment PIN_29 -to DAOUT\[5\]
set_location_assignment PIN_30 -to DAOUT4
set_location_assignment PIN_30 -to DAOUT\[4\]
set_location_assignment PIN_35 -to DAOUT3
set_location_assignment PIN_35 -to DAOUT\[3\]
set_location_assignment PIN_36 -to DAOUT2
set_location_assignment PIN_36 -to DAOUT\[2\]
set_location_assignment PIN_37 -to DAOUT1
set_location_assignment PIN_37 -to DAOUT\[1\]
set_location_assignment PIN_38 -to DAOUT0
set_location_assignment PIN_38 -to DAOUT\[0\]
set_location_assignment PIN_23 -to RDAD
set_location_assignment PIN_42 -to INTN
set_location_assignment PIN_18 -to CSAD
set_location_assignment PIN_17 -to A1
set_location_assignment PIN_17 -to A\[1\]
set_location_assignment PIN_16 -to A0
set_location_assignment PIN_16 -to A\[0\]
set_location_assignment PIN_11 -to ADIN7
set_location_assignment PIN_11 -to ADIN\[7\]
set_location_assignment PIN_10 -to ADIN6
set_location_assignment PIN_10 -to ADIN\[6\]
set_location_assignment PIN_8 -to ADIN4
set_location_assignment PIN_8 -to ADIN\[4\]
set_location_assignment PIN_7 -to ADIN3
set_location_assignment PIN_7 -to ADIN\[3\]
set_location_assignment PIN_6 -to ADIN2
set_location_assignment PIN_6 -to ADIN\[2\]
set_location_assignment PIN_5 -to ADIN1
set_location_assignment PIN_5 -to ADIN\[1\]
set_location_assignment PIN_3 -to ADIN0
set_location_assignment PIN_3 -to ADIN\[0\]
set_location_assignment PIN_1 -to CLK
set_location_assignment PIN_9 -to ADIN5
set_location_assignment PIN_9 -to ADIN\[5\]

# Timing Assignments
# ==================
set_global_assignment -name CUT_OFF_READ_DURING_WRITE_PATHS OFF

# Analysis & Synthesis Assignments
# ================================
set_global_assignment -name FAMILY FLEX10K
set_global_assignment -name TOP_LEVEL_ENTITY test_ad

# Fitter Assignments
# ==================
set_global_assignment -name DEVICE "EPF10K10LC84-4"
set_global_assignment -name AUTO_RESTART_CONFIGURATION OFF
set_global_assignment -name MAX7000B_VCCIO_IOBANK1 3.3V
set_global_assignment -name MAX7000B_VCCIO_IOBANK2 3.3V

# Timing Analysis Assignments
# ===========================
set_global_assignment -name EXCLUDE_TPD_PATHS_LESS_THAN 0.0NS

# Simulator Assignments
# =====================
set_global_assignment -name START_TIME 0.0ns
set_global_assignment -name GLITCH_INTERVAL 0.0ns
set_global_assignment -name END_TIME 20.0us