scanwave.fit.summary

来自「数字示波器的FPGA实现 VHDL编写 Quartus7.1测试通过」· SUMMARY 代码 · 共 13 行

Fitter Status : Successful - Tue Aug 28 09:56:39 2007
Quartus II Version : 7.1 Build 156 04/30/2007 SJ Web Edition
Revision Name : scanwave
Top-level Entity Name : SCANWAVE
Family : Cyclone
Device : EP1C3T144C8
Timing Models : Final
Total logic elements : 473 / 2,910 ( 16 % )
Total pins : 53 / 104 ( 51 % )
Total virtual pins : 0
Total memory bits : 32,768 / 59,904 ( 55 % )
Total PLLs : 0 / 1 ( 0 % )