sram_1.vhd

数字示波器的FPGA实现 VHDL编写 Quartus7.1测试通过

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY SRAM_1 IS
PORT(P0I: IN STD_LOGIC_VECTOR(7 DOWNTO 0);
     P0T: OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
     ALE,RD,WR,CLK: IN STD_LOGIC;
     GX: OUT STD_LOGIC;
     P2: IN STD_LOGIC_VECTOR(4 DOWNTO 0);
     DATAI: IN STD_LOGIC_VECTOR(7 DOWNTO 0);
     ADDRES: OUT STD_LOGIC_VECTOR(18 DOWNTO 0);
     DATAO: OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
     RDS,WRS,DY: OUT STD_LOGIC);
END SRAM_1;
ARCHITECTURE ART OF SRAM_1 IS

  SIGNAL RAMTMP0: STD_LOGIC_VECTOR(7 DOWNTO 0);
  SIGNAL RAMTMP1: STD_LOGIC_VECTOR(7 DOWNTO 0);
  SIGNAL RAMTMP2: STD_LOGIC_VECTOR(7 DOWNTO 0);
  SIGNAL LATCH_ADDRES: STD_LOGIC_VECTOR(7 DOWNTO 0);
  BEGIN

  PROCESS(ALE)                    
  BEGIN
  IF ALE'EVENT AND ALE='0' THEN
      LATCH_ADDRES<=P0I;
  END IF;
  END PROCESS;
ADDRES(18 DOWNTO 8)<="00000000000";
ADDRES(7 DOWNTO 0)<=LATCH_ADDRES;
RDS<=RD;
WRS<=WR;
  PROCESS(CLK,RD)
    VARIABLE P0_OUT: STD_LOGIC_VECTOR(7 DOWNTO 0);
  BEGIN
  IF (CLK'EVENT AND CLK='1') THEN
    IF( RD='0') THEN
        GX<='1';
        P0_OUT:=DATAI;
    ELSE GX<='0';
    END IF;
  END IF;
  P0T<=P0_OUT;
  END PROCESS;
  
   PROCESS(CLK,WR)
  BEGIN
  IF (CLK'EVENT AND CLK='0') THEN
    IF ( WR='0')THEN
      IF LATCH_ADDRES="11111110" THEN
          RAMTMP0<=P0I;
      ELSIF LATCH_ADDRES="11111111" THEN
          RAMTMP1<=P0I;
      ELSE RAMTMP2<=P0I;
      END IF;
    END IF;
  END IF;
  END PROCESS;
  EN<=RAMTMP1(0);

  DY<=P2(0) AND P2(1) AND P2(2) AND P2(3) AND P2(4);

  END ART;