conv_single.vhd

数字示波器的FPGA实现 VHDL编写 Quartus7.1测试通过

library IEEE;
use IEEE.std_logic_1164.all;
entity CONV_SINGLE is
	port (
	    CLK : IN STD_LOGIC;
		SINGLE : in std_logic;
--		LOCKS : IN STD_LOGIC;
	    ADDATA: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
		V0LTAGE_TRI : IN std_logic_vector (7 downto 0);
		EN : OUT STD_LOGIC;
		TRIGGER : OUT STD_LOGIC
	);
end entity;

architecture ART of CONV_SINGLE is
    TYPE STATES IS(ST0,ST1,ST2,ST3,ST4);
    SIGNAL CURRENT_STATE, NEXT_STATE: STATES:=ST0;
    SIGNAL TEMP : STD_LOGIC_VECTOR(7 DOWNTO 0);
begin

process(SINGLE,V0LTAGE_TRI,ADDATA,TEMP)
begin
        CASE CURRENT_STATE IS
        WHEN ST0=>  EN<='1';TRIGGER<='1';--LOCKS;
            IF SINGLE='0' THEN NEXT_STATE<=ST0;
            ELSE NEXT_STATE<=ST1;
            END IF;
        WHEN ST1=>  EN<='0';TRIGGER<='0'; TEMP<=V0LTAGE_TRI;
            if ( V0LTAGE_TRI = ADDATA) then NEXT_STATE<=ST2;
            ELSIF SINGLE='0' THEN NEXT_STATE<=ST0;
            ELSE NEXT_STATE<=ST1;
            END IF;
        WHEN ST2=>  EN<='0';TRIGGER<='0'; 
            if ( ADDATA > TEMP) then NEXT_STATE<=ST3;
            ELSE NEXT_STATE<=ST2;
            END IF;
        WHEN ST3=>  EN<='0';TRIGGER<='0'; 
            if ( ADDATA < TEMP) then NEXT_STATE<=ST3;
            ELSE NEXT_STATE<=ST4;
            END IF;
        WHEN ST4=>  EN<='1';TRIGGER<='1';
            IF SINGLE='1' THEN NEXT_STATE<=ST4;
            ELSE NEXT_STATE<=ST0;
            END IF;
        WHEN OTHERS=>NEXT_STATE<=ST0;
        END CASE;
END PROCESS;

PROCESS(CLK)
BEGIN
IF (CLK 'EVENT AND CLK='1') THEN
    CURRENT_STATE<=NEXT_STATE;
END IF;
END PROCESS;

end architecture;