prev_cmp_scanwave.qmsg

数字示波器的FPGA实现 VHDL编写 Quartus7.1测试通过

{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "max114.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file max114.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 MAX114-BEHAV " "Info: Found design unit 1: MAX114-BEHAV" {  } { { "max114.vhd" "" { Text "I:/数字存储示波器/scanwave/max114.vhd" 12 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "1 MAX114 " "Info: Found entity 1: MAX114" {  } { { "max114.vhd" "" { Text "I:/数字存储示波器/scanwave/max114.vhd" 4 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "VOLTAGE_CONV.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file VOLTAGE_CONV.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 VOLTAGE_CONV-ART " "Info: Found design unit 1: VOLTAGE_CONV-ART" {  } { { "VOLTAGE_CONV.vhd" "" { Text "I:/数字存储示波器/scanwave/VOLTAGE_CONV.vhd" 28 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "1 VOLTAGE_CONV " "Info: Found entity 1: VOLTAGE_CONV" {  } { { "VOLTAGE_CONV.vhd" "" { Text "I:/数字存储示波器/scanwave/VOLTAGE_CONV.vhd" 17 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "SCANWAVE.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file SCANWAVE.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 SCANWAVE " "Info: Found entity 1: SCANWAVE" {  } { { "SCANWAVE.bdf" "" { Schematic "I:/数字存储示波器/scanwave/SCANWAVE.bdf" { } } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "fredevider2.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file fredevider2.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 FREDEVIDER2-ART " "Info: Found design unit 1: FREDEVIDER2-ART" {  } { { "fredevider2.vhd" "" { Text "I:/数字存储示波器/scanwave/fredevider2.vhd" 10 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "1 FREDEVIDER2 " "Info: Found entity 1: FREDEVIDER2" {  } { { "fredevider2.vhd" "" { Text "I:/数字存储示波器/scanwave/fredevider2.vhd" 4 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0 "" 0}
{ "Error" "EVRFX_VHDL_SYNTAX_ERROR" "\"WHEN\";  expecting \"(\", or \"'\", or \".\" MUX2_3.vhd(15) " "Error (10500): VHDL syntax error at MUX2_3.vhd(15) near text \"WHEN\";  expecting \"(\", or \"'\", or \".\"" {  } { { "MUX2_3.vhd" "" { Text "I:/数字存储示波器/scanwave/MUX2_3.vhd" 15 0 0 } }  } 0 10500 "VHDL syntax error at %2!s! near text %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "MUX2_3.vhd 0 0 " "Info: Found 0 design units, including 0 entities, in source file MUX2_3.vhd" {  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "freq_count.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file freq_count.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 FREQ_COUNT-ART " "Info: Found design unit 1: FREQ_COUNT-ART" {  } { { "freq_count.vhd" "" { Text "I:/数字存储示波器/scanwave/freq_count.vhd" 15 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "1 FREQ_COUNT " "Info: Found entity 1: FREQ_COUNT" {  } { { "freq_count.vhd" "" { Text "I:/数字存储示波器/scanwave/freq_count.vhd" 6 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "fredevider10.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file fredevider10.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 FREDEVIDER10-ART " "Info: Found design unit 1: FREDEVIDER10-ART" {  } { { "fredevider10.vhd" "" { Text "I:/数字存储示波器/scanwave/fredevider10.vhd" 10 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "1 FREDEVIDER10 " "Info: Found entity 1: FREDEVIDER10" {  } { { "fredevider10.vhd" "" { Text "I:/数字存储示波器/scanwave/fredevider10.vhd" 4 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "AMPL_COUNT.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file AMPL_COUNT.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 AMPL_COUNT-ART " "Info: Found design unit 1: AMPL_COUNT-ART" {  } { { "AMPL_COUNT.vhd" "" { Text "I:/数字存储示波器/scanwave/AMPL_COUNT.vhd" 15 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "1 AMPL_COUNT " "Info: Found entity 1: AMPL_COUNT" {  } { { "AMPL_COUNT.vhd" "" { Text "I:/数字存储示波器/scanwave/AMPL_COUNT.vhd" 5 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "SCANWAVE_2.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file SCANWAVE_2.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 SCANWAVE_2 " "Info: Found entity 1: SCANWAVE_2" {  } { { "SCANWAVE_2.bdf" "" { Schematic "I:/数字存储示波器/scanwave/SCANWAVE_2.bdf" { } } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "SCANWAVE_3.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file SCANWAVE_3.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 SCANWAVE_3 " "Info: Found entity 1: SCANWAVE_3" {  } { { "SCANWAVE_3.bdf" "" { Schematic "I:/数字存储示波器/scanwave/SCANWAVE_3.bdf" { } } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0 "" 0}
{ "Error" "EQEXE_ERROR_COUNT" "Analysis & Synthesis 1  0 s Quartus II " "Error: Quartus II Analysis & Synthesis was unsuccessful. 1 error, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "147 " "Info: Allocated 147 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Error" "EQEXE_END_BANNER_TIME" "Tue Aug 28 09:55:53 2007 " "Error: Processing ended: Tue Aug 28 09:55:53 2007" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Error" "EQEXE_ELAPSED_TIME" "00:00:03 " "Error: Elapsed time: 00:00:03" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0}  } {  } 0 0 "%6!s! %1!s! was unsuccessful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}
{ "Error" "EFLOW_ERROR_COUNT" "Full Compilation 1  0 s " "Error: Quartus II Full Compilation was unsuccessful. 1 error, 0 warnings" {  } {  } 0 0 "Quartus II %1!s! was unsuccessful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}