scanwave.fit.eqn

数字示波器的FPGA实现 VHDL编写 Quartus7.1测试通过

V2_q_b[4] = V2_q_b[7]_PORT_B_data_out[1];


--H1_RAMTMP5[7] is BUS_1:inst5|RAMTMP5[7] at LC_X16_Y2_N9
--operation mode is normal

H1_RAMTMP5[7]_lut_out = X1_q_a[5] & (H1_RAMTMP5[7] # H1L69 & A1L84) # !X1_q_a[5] & H1L69 & A1L84;
H1_RAMTMP5[7] = DFFEA(H1_RAMTMP5[7]_lut_out, !GLOBAL(CLK), VCC, , H1L92, , );


--L2L44 is VOLTAGE_CONV:inst17|LessThan~7COUT0 at LC_X19_Y3_N6
--operation mode is arithmetic

L2L44_cout_0 = L2L51 & V2_q_b[6] & !L2L04 # !L2L51 & (V2_q_b[6] # !L2L04);
L2L44 = CARRY(L2L44_cout_0);

--L2L54 is VOLTAGE_CONV:inst17|LessThan~7COUT1 at LC_X19_Y3_N6
--operation mode is arithmetic

L2L54_cout_1 = L2L51 & V2_q_b[6] & !L2L14 # !L2L51 & (V2_q_b[6] # !L2L14);
L2L54 = CARRY(L2L54_cout_1);


--V1_q_b[6] is dram:inst|altsyncram:altsyncram_component|altsyncram_3771:auto_generated|q_b[6] at M4K_X13_Y6
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 2048, Port A Width: 2, Port B Depth: 2048, Port B Width: 2
--Port A Logical Depth: 2048, Port A Logical Width: 8, Port B Logical Depth: 2048, Port B Logical Width: 8
--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered
V1_q_b[6]_PORT_A_data_in = BUS(R1_data[6], R1_data[5]);
V1_q_b[6]_PORT_A_data_in_reg = DFFE(V1_q_b[6]_PORT_A_data_in, V1_q_b[6]_clock_0, , , );
V1_q_b[6]_PORT_A_address = BUS(R1_cnt2[0], R1_cnt2[1], R1_cnt2[2], R1_cnt2[3], R1_cnt2[4], R1_cnt2[5], R1_cnt2[6], R1_cnt2[7], R1_cnt2[8], R1_cnt2[9], R1_cnt2[10]);
V1_q_b[6]_PORT_A_address_reg = DFFE(V1_q_b[6]_PORT_A_address, V1_q_b[6]_clock_0, , , );
V1_q_b[6]_PORT_B_address = BUS(M1_COUNTER[0], M1_COUNTER[1], M1_COUNTER[2], M1_COUNTER[3], M1_COUNTER[4], M1_COUNTER[5], M1_COUNTER[6], M1_COUNTER[7], M1_COUNTER[8], M1_COUNTER[9], M1_COUNTER[10]);
V1_q_b[6]_PORT_B_address_reg = DFFE(V1_q_b[6]_PORT_B_address, V1_q_b[6]_clock_1, , , );
V1_q_b[6]_PORT_A_write_enable = VCC;
V1_q_b[6]_PORT_A_write_enable_reg = DFFE(V1_q_b[6]_PORT_A_write_enable, V1_q_b[6]_clock_0, , , );
V1_q_b[6]_PORT_B_read_enable = VCC;
V1_q_b[6]_PORT_B_read_enable_reg = DFFE(V1_q_b[6]_PORT_B_read_enable, V1_q_b[6]_clock_1, , , );
V1_q_b[6]_clock_0 = GLOBAL(CLK);
V1_q_b[6]_clock_1 = GLOBAL(CLK);
V1_q_b[6]_PORT_B_data_out = MEMORY(V1_q_b[6]_PORT_A_data_in_reg, , V1_q_b[6]_PORT_A_address_reg, V1_q_b[6]_PORT_B_address_reg, V1_q_b[6]_PORT_A_write_enable_reg, V1_q_b[6]_PORT_B_read_enable_reg, , , V1_q_b[6]_clock_0, V1_q_b[6]_clock_1, , , , );
V1_q_b[6] = V1_q_b[6]_PORT_B_data_out[0];

--V1_q_b[5] is dram:inst|altsyncram:altsyncram_component|altsyncram_3771:auto_generated|q_b[5] at M4K_X13_Y6
V1_q_b[6]_PORT_A_data_in = BUS(R1_data[6], R1_data[5]);
V1_q_b[6]_PORT_A_data_in_reg = DFFE(V1_q_b[6]_PORT_A_data_in, V1_q_b[6]_clock_0, , , );
V1_q_b[6]_PORT_A_address = BUS(R1_cnt2[0], R1_cnt2[1], R1_cnt2[2], R1_cnt2[3], R1_cnt2[4], R1_cnt2[5], R1_cnt2[6], R1_cnt2[7], R1_cnt2[8], R1_cnt2[9], R1_cnt2[10]);
V1_q_b[6]_PORT_A_address_reg = DFFE(V1_q_b[6]_PORT_A_address, V1_q_b[6]_clock_0, , , );
V1_q_b[6]_PORT_B_address = BUS(M1_COUNTER[0], M1_COUNTER[1], M1_COUNTER[2], M1_COUNTER[3], M1_COUNTER[4], M1_COUNTER[5], M1_COUNTER[6], M1_COUNTER[7], M1_COUNTER[8], M1_COUNTER[9], M1_COUNTER[10]);
V1_q_b[6]_PORT_B_address_reg = DFFE(V1_q_b[6]_PORT_B_address, V1_q_b[6]_clock_1, , , );
V1_q_b[6]_PORT_A_write_enable = VCC;
V1_q_b[6]_PORT_A_write_enable_reg = DFFE(V1_q_b[6]_PORT_A_write_enable, V1_q_b[6]_clock_0, , , );
V1_q_b[6]_PORT_B_read_enable = VCC;
V1_q_b[6]_PORT_B_read_enable_reg = DFFE(V1_q_b[6]_PORT_B_read_enable, V1_q_b[6]_clock_1, , , );
V1_q_b[6]_clock_0 = GLOBAL(CLK);
V1_q_b[6]_clock_1 = GLOBAL(CLK);
V1_q_b[6]_PORT_B_data_out = MEMORY(V1_q_b[6]_PORT_A_data_in_reg, , V1_q_b[6]_PORT_A_address_reg, V1_q_b[6]_PORT_B_address_reg, V1_q_b[6]_PORT_A_write_enable_reg, V1_q_b[6]_PORT_B_read_enable_reg, , , V1_q_b[6]_clock_0, V1_q_b[6]_clock_1, , , , );
V1_q_b[5] = V1_q_b[6]_PORT_B_data_out[1];


--H1_RAMTMP2[6] is BUS_1:inst5|RAMTMP2[6] at LC_X18_Y2_N9
--operation mode is normal

H1_RAMTMP2[6]_lut_out = X1_q_a[6] & (H1_RAMTMP2[6] # H1L59 & A1L94) # !X1_q_a[6] & H1L59 & A1L94;
H1_RAMTMP2[6] = DFFEA(H1_RAMTMP2[6]_lut_out, !GLOBAL(CLK), VCC, , H1L92, , );


--V2_q_b[6] is dram:inst14|altsyncram:altsyncram_component|altsyncram_3771:auto_generated|q_b[6] at M4K_X13_Y4
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 2048, Port A Width: 2, Port B Depth: 2048, Port B Width: 2
--Port A Logical Depth: 2048, Port A Logical Width: 8, Port B Logical Depth: 2048, Port B Logical Width: 8
--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered
V2_q_b[6]_PORT_A_data_in = BUS(R2_data[6], R2_data[5]);
V2_q_b[6]_PORT_A_data_in_reg = DFFE(V2_q_b[6]_PORT_A_data_in, V2_q_b[6]_clock_0, , , );
V2_q_b[6]_PORT_A_address = BUS(R2_cnt2[0], R2_cnt2[1], R2_cnt2[2], R2_cnt2[3], R2_cnt2[4], R2_cnt2[5], R2_cnt2[6], R2_cnt2[7], R2_cnt2[8], R2_cnt2[9], R2_cnt2[10]);
V2_q_b[6]_PORT_A_address_reg = DFFE(V2_q_b[6]_PORT_A_address, V2_q_b[6]_clock_0, , , );
V2_q_b[6]_PORT_B_address = BUS(M1_COUNTER[0], M1_COUNTER[1], M1_COUNTER[2], M1_COUNTER[3], M1_COUNTER[4], M1_COUNTER[5], M1_COUNTER[6], M1_COUNTER[7], M1_COUNTER[8], M1_COUNTER[9], M1_COUNTER[10]);
V2_q_b[6]_PORT_B_address_reg = DFFE(V2_q_b[6]_PORT_B_address, V2_q_b[6]_clock_1, , , );
V2_q_b[6]_PORT_A_write_enable = VCC;
V2_q_b[6]_PORT_A_write_enable_reg = DFFE(V2_q_b[6]_PORT_A_write_enable, V2_q_b[6]_clock_0, , , );
V2_q_b[6]_PORT_B_read_enable = VCC;
V2_q_b[6]_PORT_B_read_enable_reg = DFFE(V2_q_b[6]_PORT_B_read_enable, V2_q_b[6]_clock_1, , , );
V2_q_b[6]_clock_0 = GLOBAL(CLK);
V2_q_b[6]_clock_1 = GLOBAL(CLK);
V2_q_b[6]_PORT_B_data_out = MEMORY(V2_q_b[6]_PORT_A_data_in_reg, , V2_q_b[6]_PORT_A_address_reg, V2_q_b[6]_PORT_B_address_reg, V2_q_b[6]_PORT_A_write_enable_reg, V2_q_b[6]_PORT_B_read_enable_reg, , , V2_q_b[6]_clock_0, V2_q_b[6]_clock_1, , , , );
V2_q_b[6] = V2_q_b[6]_PORT_B_data_out[0];

--V2_q_b[5] is dram:inst14|altsyncram:altsyncram_component|altsyncram_3771:auto_generated|q_b[5] at M4K_X13_Y4
V2_q_b[6]_PORT_A_data_in = BUS(R2_data[6], R2_data[5]);
V2_q_b[6]_PORT_A_data_in_reg = DFFE(V2_q_b[6]_PORT_A_data_in, V2_q_b[6]_clock_0, , , );
V2_q_b[6]_PORT_A_address = BUS(R2_cnt2[0], R2_cnt2[1], R2_cnt2[2], R2_cnt2[3], R2_cnt2[4], R2_cnt2[5], R2_cnt2[6], R2_cnt2[7], R2_cnt2[8], R2_cnt2[9], R2_cnt2[10]);
V2_q_b[6]_PORT_A_address_reg = DFFE(V2_q_b[6]_PORT_A_address, V2_q_b[6]_clock_0, , , );
V2_q_b[6]_PORT_B_address = BUS(M1_COUNTER[0], M1_COUNTER[1], M1_COUNTER[2], M1_COUNTER[3], M1_COUNTER[4], M1_COUNTER[5], M1_COUNTER[6], M1_COUNTER[7], M1_COUNTER[8], M1_COUNTER[9], M1_COUNTER[10]);
V2_q_b[6]_PORT_B_address_reg = DFFE(V2_q_b[6]_PORT_B_address, V2_q_b[6]_clock_1, , , );
V2_q_b[6]_PORT_A_write_enable = VCC;
V2_q_b[6]_PORT_A_write_enable_reg = DFFE(V2_q_b[6]_PORT_A_write_enable, V2_q_b[6]_clock_0, , , );
V2_q_b[6]_PORT_B_read_enable = VCC;
V2_q_b[6]_PORT_B_read_enable_reg = DFFE(V2_q_b[6]_PORT_B_read_enable, V2_q_b[6]_clock_1, , , );
V2_q_b[6]_clock_0 = GLOBAL(CLK);
V2_q_b[6]_clock_1 = GLOBAL(CLK);
V2_q_b[6]_PORT_B_data_out = MEMORY(V2_q_b[6]_PORT_A_data_in_reg, , V2_q_b[6]_PORT_A_address_reg, V2_q_b[6]_PORT_B_address_reg, V2_q_b[6]_PORT_A_write_enable_reg, V2_q_b[6]_PORT_B_read_enable_reg, , , V2_q_b[6]_clock_0, V2_q_b[6]_clock_1, , , , );
V2_q_b[5] = V2_q_b[6]_PORT_B_data_out[1];


--H1_RAMTMP5[6] is BUS_1:inst5|RAMTMP5[6] at LC_X16_Y2_N2
--operation mode is normal

H1_RAMTMP5[6]_lut_out = X1_q_a[5] & (H1_RAMTMP5[6] # H1L69 & A1L94) # !X1_q_a[5] & H1L69 & A1L94;
H1_RAMTMP5[6] = DFFEA(H1_RAMTMP5[6]_lut_out, !GLOBAL(CLK), VCC, , H1L92, , );


--H1_RAMTMP2[5] is BUS_1:inst5|RAMTMP2[5] at LC_X18_Y2_N1
--operation mode is normal

H1_RAMTMP2[5]_lut_out = H1_RAMTMP2[5] & (X1_q_a[6] # H1L59 & A1L05) # !H1_RAMTMP2[5] & H1L59 & A1L05;
H1_RAMTMP2[5] = DFFEA(H1_RAMTMP2[5]_lut_out, !GLOBAL(CLK), VCC, , H1L92, , );


--H1_RAMTMP5[5] is BUS_1:inst5|RAMTMP5[5] at LC_X16_Y2_N8
--operation mode is normal

H1_RAMTMP5[5]_lut_out = X1_q_a[5] & (H1_RAMTMP5[5] # H1L69 & A1L05) # !X1_q_a[5] & H1L69 & A1L05;
H1_RAMTMP5[5] = DFFEA(H1_RAMTMP5[5]_lut_out, !GLOBAL(CLK), VCC, , H1L92, , );


--V1_q_b[4] is dram:inst|altsyncram:altsyncram_component|altsyncram_3771:auto_generated|q_b[4] at M4K_X13_Y8
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 2048, Port A Width: 2, Port B Depth: 2048, Port B Width: 2
--Port A Logical Depth: 2048, Port A Logical Width: 8, Port B Logical Depth: 2048, Port B Logical Width: 8
--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered
V1_q_b[4]_PORT_A_data_in = BUS(R1_data[4], R1_data[1]);
V1_q_b[4]_PORT_A_data_in_reg = DFFE(V1_q_b[4]_PORT_A_data_in, V1_q_b[4]_clock_0, , , );
V1_q_b[4]_PORT_A_address = BUS(R1_cnt2[0], R1_cnt2[1], R1_cnt2[2], R1_cnt2[3], R1_cnt2[4], R1_cnt2[5], R1_cnt2[6], R1_cnt2[7], R1_cnt2[8], R1_cnt2[9], R1_cnt2[10]);
V1_q_b[4]_PORT_A_address_reg = DFFE(V1_q_b[4]_PORT_A_address, V1_q_b[4]_clock_0, , , );
V1_q_b[4]_PORT_B_address = BUS(M1_COUNTER[0], M1_COUNTER[1], M1_COUNTER[2], M1_COUNTER[3], M1_COUNTER[4], M1_COUNTER[5], M1_COUNTER[6], M1_COUNTER[7], M1_COUNTER[8], M1_COUNTER[9], M1_COUNTER[10]);
V1_q_b[4]_PORT_B_address_reg = DFFE(V1_q_b[4]_PORT_B_address, V1_q_b[4]_clock_1, , , );
V1_q_b[4]_PORT_A_write_enable = VCC;
V1_q_b[4]_PORT_A_write_enable_reg = DFFE(V1_q_b[4]_PORT_A_write_enable, V1_q_b[4]_clock_0, , , );
V1_q_b[4]_PORT_B_read_enable = VCC;
V1_q_b[4]_PORT_B_read_enable_reg = DFFE(V1_q_b[4]_PORT_B_read_enable, V1_q_b[4]_clock_1, , , );
V1_q_b[4]_clock_0 = GLOBAL(CLK);
V1_q_b[4]_clock_1 = GLOBAL(CLK);
V1_q_b[4]_PORT_B_data_out = MEMORY(V1_q_b[4]_PORT_A_data_in_reg, , V1_q_b[4]_PORT_A_address_reg, V1_q_b[4]_PORT_B_address_reg, V1_q_b[4]_PORT_A_write_enable_reg, V1_q_b[4]_PORT_B_read_enable_reg, , , V1_q_b[4]_clock_0, V1_q_b[4]_clock_1, , , , );
V1_q_b[4] = V1_q_b[4]_PORT_B_data_out[0];

--V1_q_b[1] is dram:inst|altsyncram:altsyncram_component|altsyncram_3771:auto_generated|q_b[1] at M4K_X13_Y8
V1_q_b[4]_PORT_A_data_in = BUS(R1_data[4], R1_data[1]);
V1_q_b[4]_PORT_A_data_in_reg = DFFE(V1_q_b[4]_PORT_A_data_in, V1_q_b[4]_clock_0, , , );
V1_q_b[4]_PORT_A_address = BUS(R1_cnt2[0], R1_cnt2[1], R1_cnt2[2], R1_cnt2[3], R1_cnt2[4], R1_cnt2[5], R1_cnt2[6], R1_cnt2[7], R1_cnt2[8], R1_cnt2[9], R1_cnt2[10]);
V1_q_b[4]_PORT_A_address_reg = DFFE(V1_q_b[4]_PORT_A_address, V1_q_b[4]_clock_0, , , );
V1_q_b[4]_PORT_B_address = BUS(M1_COUNTER[0], M1_COUNTER[1], M1_COUNTER[2], M1_COUNTER[3], M1_COUNTER[4], M1_COUNTER[5], M1_COUNTER[6], M1_COUNTER[7], M1_COUNTER[8], M1_COUNTER[9], M1_COUNTER[10]);
V1_q_b[4]_PORT_B_address_reg = DFFE(V1_q_b[4]_PORT_B_address, V1_q_b[4]_clock_1, , , );
V1_q_b[4]_PORT_A_write_enable = VCC;
V1_q_b[4]_PORT_A_write_enable_reg = DFFE(V1_q_b[4]_PORT_A_write_enable, V1_q_b[4]_clock_0, , , );
V1_q_b[4]_PORT_B_read_enable = VCC;
V1_q_b[4]_PORT_B_read_enable_reg = DFFE(V1_q_b[4]_PORT_B_read_enable, V1_q_b[4]_clock_1, , , );
V1_q_b[4]_clock_0 = GLOBAL(CLK);
V1_q_b[4]_clock_1 = GLOBAL(CLK);
V1_q_b[4]_PORT_B_data_out = MEMORY(V1_q_b[4]_PORT_A_data_in_reg, , V1_q_b[4]_PORT_A_address_reg, V1_q_b[4]_PORT_B_address_reg, V1_q_b[4]_PORT_A_write_enable_reg, V1_q_b[4]_PORT_B_read_enable_reg, , , V1_q_b[4]_clock_0, V1_q_b[4]_clock_1, , , , );
V1_q_b[1] = V1_q_b[4]_PORT_B_data_out[1];


--H1_RAMTMP2[4] is BUS_1:inst5|RAMTMP2[4] at LC_X18_Y2_N4
--operation mode is normal

H1_RAMTMP2[4]_lut_out = X1_q_a[6] & (H1_RAMTMP2[4] # A1L15 & H1L59) # !X1_q_a[6] & A1L15 & H1L59;
H1_RAMTMP2[4] = DFFEA(H1_RAMTMP2[4]_lut_out, !GLOBAL(CLK), VCC, , H1L92, , );


--H1_RAMTMP5[4] is BUS_1:inst5|RAMTMP5[4] at LC_X16_Y2_N3
--operation mode is normal

H1_RAMTMP5[4]_lut_out = X1_q_a[5] & (H1_RAMTMP5[4] # H1L69 & A1L15) # !X1_q_a[5] & H1L69 & A1L15;
H1_RAMTMP5[4] = DFFEA(H1_RAMTMP5[4]_lut_out, !GLOBAL(CLK), VCC, , H1L92, , );


--V1_q_b[3] is dram:inst|altsyncram:altsyncram_component|altsyncram_3771:auto_generated|q_b[3] at M4K_X13_Y9
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 2048, Port A Width: 2, Port B Depth: 2048, Port B Width: 2
--Port A Logical Depth: 2048, Port A Logical Width: 8, Port B Logical Depth: 2048, Port B Logical Width: 8
--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered
V1_q_b[3]_PORT_A_data_in = BUS(R1_data[3], R1_data[0]);
V1_q_b[3]_PORT_A_data_in_reg = DFFE(V1_q_b[3]_PORT_A_data_in, V1_q_b[3]_clock_0, , , );
V1_q_b[3]_PORT_A_address = BUS(R1_cnt2[0], R1_cnt2[1], R1_cnt2[2], R1_cnt2[3], R1_cnt2[4], R1_cnt2[5], R1_cnt2[6], R1_cnt2[7], R1_cnt2[8], R1_cnt2[9], R1_cnt2[10]);
V1_q_b[3]_PORT_A_address_reg = DFFE(V1_q_b[3]_PORT_A_address, V1_q_b[3]_clock_0, , , );
V1_q_b[3]_PORT_B_address = BUS(M1_COUNTER[0], M1_COUNTER[1], M1_COUNTER[2], M1_COUNTER[3], M1_COUNTER[4], M1_COUNTER[5], M1_COUNTER[6], M1_COUNTER[7], M1_COUNTER[8], M1_COUNTER[9], M1_COUNTER[10]);
V1_q_b[3]_PORT_B_address_reg = DFFE(V1_q_b[3]_PORT_B_address, V1_q_b[3]_clock_1, , , );
V1_q_b[3]_PORT_A_write_enable = VCC;
V1_q_b[3]_PORT_A_write_enable_reg = DFFE(V1_q_b[3]_PORT_A_write_enable, V1_q_b[3]_clock_0, , , );
V1_q_b[3]_PORT_B_read_enable = VCC;
V1_q_b[3]_PORT_B_read_enable_reg = DFFE(V1_q_b[3]_PORT_B_read_enable, V1_q_b[3]_clock_1, , , );
V1_q_b[3]_clock_0 = GLOBAL(CLK);
V1_q_b[3]_clock_1 = GLOBAL(CLK);
V1_q_b[3]_PORT_B_data_out = MEMORY(V1_q_b[3]_PORT_A_data_in_reg, , V1_q_b[3]_PORT_A_address_reg, V1_q_b[3]_PORT_B_address_reg, V1_q_b[3]_PORT_A_write_enable_reg, V1_q_b[3]_PORT_B_read_enable_reg, , , V1_q_b[3]_clock_0, V1_q_b[3]_clock_1, , , , );
V1_q_b[3] = V1_q_b[3]_PORT_B_data_out[0];

--V1_q_b[0] is dram:inst|altsyncram:altsyncram_component|altsyncram_3771:auto_generated|q_b[0] at M4K_X13_Y9
V1_q_b[3]_PORT_A_data_in = BUS(R1_data[3], R1_data[0]);
V1_q_b[3]_PORT_A_data_in_reg = DFFE(V1_q_b[3]_PORT_A_data_in, V1_q_b[3]_clock_0, , , );
V1_q_b[3]_PORT_A_address = BUS(R1_cnt2[0], R1_cnt2[1], R1_cnt2[2], R1_cnt2[3], R1_cnt2[4], R1_cnt2[5], R1_cnt2[6], R1_cnt2[7], R1_cnt2[8], R1_cnt2[9], R1_cnt2[10]);
V1_q_b[3]_PORT_A_address_reg = DFFE(V1_q_b[3]_PORT_A_address, V1_q_b[3]_clock_0, , , );
V1_q_b[3]_PORT_B_address = BUS(M1_COUNTER[0], M1_COUNTER[1], M1_COUNTER[2], M1_COUNTER[3], M1_COUNTER[4], M1_COUNTER[5], M1_COUNTER[6], M1_COUNTER[7], M1_COUNTER[8], M1_COUNTER[9], M1_COUNTER[10]);
V1_q_b[3]_PORT_B_address_reg = DFFE(V1_q_b[3]_PORT_B_address, V1_q_b[3]_clock_1, , , );
V1_q_b[3]_PORT_A_write_enable = VCC;
V1_q_b[3]_PORT_A_write_enable_reg = DFFE(V1_q_b[3]_PORT_A_write_enable, V1_q_b[3]_clock_0, , , );
V1_q_b[3]_PORT_B_read_enable = VCC;
V1_q_b[3]_PORT_B_read_enable_reg = DFFE(V1_q_b[3]_PORT_B_read_enable, V1_q_b[3]_clock_1, , , );
V1_q_b[3]_clock_0 = GLOBAL(CLK);
V1_q_b[3]_clock_1 = GLOBAL(CLK);
V1_q_b[3]_PORT_B_data_out = MEMORY(V1_q_b[3]_PORT_A_data_in_reg, , V1_q_b[3]_PORT_A_address_reg, V1_q_b[3]_PORT_B_address_reg, V1_q_b[3]_PORT_A_write_enable_reg, V1_q_b[3]_PORT_B_read_enable_reg, , , V1_q_b[3]_clock_0, V1_q_b[3]_clock_1, , , , );
V1_q_b[0] = V1_q_b[3]_PORT_B_data_out[1];


--H1_RAMTMP2[3] is BUS_1:inst5|RAMTMP2[3] at LC_X18_Y2_N0
--operation mode is normal

H1_RAMTMP2[3]_lut_out = X1_q_a[6] & (H1_RAMTMP2[3] # A1L25 & H1L59) # !X1_q_a[6] & A1L25 & H1L59;
H1_RAMTMP2[3] = DFFEA(H1_RAMTMP2[3]_lut_out, !GLOBAL(CLK), VCC, , H1L92, , );


--V2_q_b[3] is dram:inst14|altsyncram:altsyncram_component|altsyncram_3771:auto_generated|q_b[3] at M4K_X13_Y3
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 2048, Port A Width: 2, Port B Depth: 2048, Port B Width: 2
--Port A Logical Depth: 2048, Port A Logical Width: 8, Port B Logical Depth: 2048, Port B Logical Width: 8
--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered
V2_q_b[3]_PORT_A_data_in = BUS(R2_data[3], R2_data[2]);
V2_q_b[3]_PORT_A_data_in_reg = DFFE(V2_q_b[3]_PORT_A_data_in, V2_q_b[3]_clock_0, , , );
V2_q_b[3]_PORT_A_address = BUS(R2_cnt2[0], R2_cnt2[1], R2_cnt2[2], R2_cnt2[3], R2_cnt2[4], R2_cnt2[5], R2_cnt2[6], R2_cnt2[7], R2_cnt2[8], R2_cnt2[9], R2_cnt2[10]);
V2_q_b[3]_PORT_A_address_reg = DFFE(V2_q_b[3]_PORT_A_address, V2_q_b[3]_clock_0, , , );
V2_q_b[3]_PORT_B_address = BUS(M1_COUNTER[0], M1_COUNTER[1], M1_COUNTER[2], M1_COUNTER[3], M1_COUNTER[4], M1_COUNTER[5], M1_COUNTER[6], M1_COUNTER[7], M1_COUNTER[8], M1_COUNTER[9], M1_COUNTER[10]);
V2_q_b[3]_PORT_B_address_reg = DFFE(V2_q_b[3]_PORT_B_address, V2_q_b[3]_clock_1, , , );
V2_q_b[3]_PORT_A_write_enable = VCC;
V2_q_b[3]_PORT_A_write_enable_reg = DFFE(V2_q_b[3]_PORT_A_write_enable, V2_q_b[3]_clock_0, , , );
V2_q_b[3]_PORT_B_read_enable = VCC;
V2_q_b[3]_PORT_B_read_enable_reg = DFFE(V2_q_b[3]_PORT_B_read_enable, V2_q_b[3]_clock_1, , , );
V2_q_b[3]_clock_0 = GLOBAL(CLK);
V2_q_b[3]_clock_1 = GLOBAL(CLK);
V2_q_b[3]_PORT_B_data_out = MEMORY(V2_q_b[3]_PORT_A_data_in_reg, , V2_q_b[3]_PORT_A_address_reg, V2_q_b[3]_PORT_B_address_reg, V2_q_b[3]_PORT_A_write_enable_reg, V2_q_b[3]_PORT_B_read_enable_reg, , , V2_q_b[3]_clock_0, V2_q_b[3]_clock_1, , , , );
V2_q_b[3] = V2_q_b[3]_PORT_B_data_out[0];

--V2_q_b[2] is dram:inst14|altsyncram:altsyncram_component|altsyncram_3771:auto_generated|q_b[2] at M4K_X13_Y3
V2_q_b[3]_PORT_A_data_in = BUS(R2_data[3], R2_data[2]);
V2_q_b[3]_PORT_A_data_in_reg = DFFE(V2_q_b[3]_PORT_A_data_in, V2_q_b[3]_clock_0, , , );
V2_q_b[3]_PORT_A_address = BUS(R2_cnt2[0], R2_cnt2[1], R2_cnt2[2], R2_cnt2[3], R2_cnt2[4], R2_cnt2[5], R2_cnt2[6], R2_cnt2[7], R2_cnt2[8], R2_cnt2[9], R2_cnt2[10]);
V2_q_b[3]_PORT_A_address_reg = DFFE(V2_q_b[3]_PORT_A_address, V2_q_b[3]_clock_0, , , );
V2_q_b[3]_PORT_B_address = BUS(M1_COUNTER[0], M1_COUNTER[1], M1_COUNTER[2], M1_COUNTER[3], M1_COUNTER[4], M1_COUNTER[5], M1_COUNTER[6], M1_COUNTER[7], M1_COUNTER[8], M1_COUNTER[9], M1_COUNTER[10]);
V2_q_b[3]_PORT_B_address_reg = DFFE(V2_q_b[3]_PORT_B_address, V2_q_b[3]_clock_1, , , );
V2_q_b[3]_PORT_A_write_enable = VCC;
V2_q_b[3]_PORT_A_write_enable_reg = DFFE(V2_q_b[3]_PORT_A_write_enable, V2_q_b[3]_clock_0, , , );
V2_q_b[3]_PORT_B_read_enable = VCC;
V2_q_b[3]_PORT_B_read_enable_reg = DFFE(V2_q_b[3]_PORT_B_read_enable, V2_q_b[3]_clock_1, , , );
V2_q_b[3]_clock_0 = GLOBAL(CLK);
V2_q_b[3]_clock_1 = GLOBAL(CLK);
V2_q_b[3]_PORT_B_data_out = MEMORY(V2_q_b[3]_PORT_A_data_in_reg, , V2_q_b[3]_PORT_A_address_reg, V2_q_b[3]_PORT_B_address_reg, V2_q_b[3]_PORT_A_write_enable_reg, V2_q_b[3]_PORT_B_read_enable_reg, , , V2_q_b[3]_clock_0, V2_q_b[3]_clock_1, , , , );
V2_q_b[2] = V2_q_b[3]_PORT_B_data_out[1];


--H1_RAMTMP5[3] is BUS_1:inst5|RAMTMP5[3] at LC_X16_Y2_N6
--operation mode is normal

H1_RAMTMP5[3]_lut_out = X1_q_a[5] & (H1_RAMTMP5[3] # A1L25 & H1L69) # !X1_q_a[5] & A1L25 & H1L69;
H1_RAMTMP5[3] = DFFEA(H1_RAMTMP5[3]_lut_out, !GLOBAL(CLK), VCC, , H1L92, , );


--H1_RAMTMP2[2] is BUS_1:inst5|RAMTMP2[2] at LC_X18_Y2_N8
--operation mode is normal

H1_RAMTMP2[2]_lut_out = A1L35 & (H1L59 # H1_RAMTMP2[2] & X1_q_a[6]) # !A1L35 & H1_RAMTMP2[2] & X1_q_a[6];
H1_RAMTMP2[2] = DFFEA(H1_RAMTMP2[2]_lut_out, !GLOBAL(CLK), VCC, , H1L92, , );


--H1_RAMTMP5[2] is BUS_1:inst5|RAMTMP5[2] at LC_X16_Y2_N0
--operation mode is normal

H1_RAMTMP5[2]_lut_out = X1_q_a[5] & (H1_RAMTMP5[2] # H1L69 & A1L35) # !X1_q_a[5] & H1L69 & A1L35;
H1_RAMTMP5[2] = DFFEA(H1_RAMTMP5[2]_lut_out, !GLOBAL(CLK), VCC, , H1L92, , );


--H1_RAMTMP2[1] is BUS_1:inst5|RAMTMP2[1] at LC_X18_Y4_N8
--operation mode is normal

H1_RAMTMP2[1]_lut_out = X1_q_a[6] & (H1_RAMTMP2[1] # H1L59 & A1L45) # !X1_q_a[6] & H1L59 & A1L45;
H1_RAMTMP2[1] = DFFEA(H1_RAMTMP2[1]_lut_out, !GLOBAL(CLK), VCC, , H1L92, , );


--V2_q_b[1] is dram:inst14|altsyncram:altsyncram_component|altsyncram_3771:auto_generated|q_b[1] at M4K_X13_Y2
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 2048, Port A Width: 2, Port B Depth: 2048, Port B Width: 2
--Port A Logical Depth: 2048, Port A Logical Width: 8, Port B Logical Depth: 2048, Port B Logical Width: 8
--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered
V2_q_b[1]_PORT_A_data_in = BUS(R2_data[1], R2_data[0]);
V2_q_b[1]_PORT_A_data_in_reg = DFFE(V2_q_b[1]_PORT_A_data_in, V2_q_b[1]_clock_0, , , );
V2_q_b[1]_PORT_A_address = BUS(R2_cnt2[0], R2_cnt2[1], R2_cnt2[2], R2_cnt2[3], R2_cnt2[4], R2_cnt2[5], R2_cnt2[6], R2_cnt2[7], R2_cnt2[8], R2_cnt2[9], R2_cnt2[10]);
V2_q_b[1]_PORT_A_address_reg = DFFE(V2_q_b[1]_PORT_A_address, V2_q_b[1]_clock_0, , , );
V2_q_b[1]_PORT_B_address = BUS(M1_COUNTER[0], M1_COUNTER[1], M1_COUNTER[2], M1_COUNTER[3], M1_COUNTER[4], M1_COUNTER[5], M1_COUNTER[6], M1_COUNTER[7], M1_COUNTER[8], M1_COUNTER[9], M1_COUNTER[10]);
V2_q_b[1]_PORT_B_address_reg = DFFE(V2_q_b[1]_PORT_B_address, V2_q_b[1]_clock_1, , , );
V2_q_b[1]_PORT_A_write_enable = VCC;
V2_q_b[1]_PORT_A_write_enable_reg = DFFE(V2_q_b[1]_PORT_A_write_enable, V2_q_b[1]_clock_0, , , );
V2_q_b[1]_PORT_B_read_enable = VCC;
V2_q_b[1]_PORT_B_read_enable_reg = DFFE(V2_q_b[1]_PORT_B_read_enable, V2_q_b[1]_clock_1, , , );
V2_q_b[1]_clock_0 = GLOBAL(CLK);
V2_q_b[1]_clock_1 = GLOBAL(CLK);
V2_q_b[1]_PORT_B_data_out = MEMORY(V2_q_b[1]_PORT_A_data_in_reg, , V2_q_b[1]_PORT_A_address_reg, V2_q_b[1]_PORT_B_address_reg, V2_q_b[1]_PORT_A_writ