scanwave.fit.eqn

数字示波器的FPGA实现 VHDL编写 Quartus7.1测试通过

--operation mode is arithmetic

G1L06_cout_1 = G1_REG_Q[16] & !G1L65;
G1L06 = CARRY(G1L06_cout_1);


--G1L55 is generator_accB:inst4|add~16 at LC_X10_Y2_N9
--operation mode is arithmetic

G1L55_carry_eqn = (!G1L83 & G1L35) # (G1L83 & G1L45);
G1L55 = G1_REG_Q[15] $ H1_RAMTMP9[7] $ G1L55_carry_eqn;

--G1L65 is generator_accB:inst4|add~16COUT at LC_X10_Y2_N9
--operation mode is arithmetic

G1L65 = CARRY(G1_REG_Q[15] & !H1_RAMTMP9[7] & !G1L45 # !G1_REG_Q[15] & (!G1L45 # !H1_RAMTMP9[7]));


--G1L15 is generator_accB:inst4|add~15 at LC_X10_Y2_N8
--operation mode is arithmetic

G1L15_carry_eqn = (!G1L83 & G1L94) # (G1L83 & G1L05);
G1L15 = H1_RAMTMP9[6] $ G1_REG_Q[14] $ !G1L15_carry_eqn;

--G1L35 is generator_accB:inst4|add~15COUT0 at LC_X10_Y2_N8
--operation mode is arithmetic

G1L35_cout_0 = H1_RAMTMP9[6] & (G1_REG_Q[14] # !G1L94) # !H1_RAMTMP9[6] & G1_REG_Q[14] & !G1L94;
G1L35 = CARRY(G1L35_cout_0);

--G1L45 is generator_accB:inst4|add~15COUT1 at LC_X10_Y2_N8
--operation mode is arithmetic

G1L45_cout_1 = H1_RAMTMP9[6] & (G1_REG_Q[14] # !G1L05) # !H1_RAMTMP9[6] & G1_REG_Q[14] & !G1L05;
G1L45 = CARRY(G1L45_cout_1);


--V1_q_b[7] is dram:inst|altsyncram:altsyncram_component|altsyncram_3771:auto_generated|q_b[7] at M4K_X13_Y7
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 2048, Port A Width: 2, Port B Depth: 2048, Port B Width: 2
--Port A Logical Depth: 2048, Port A Logical Width: 8, Port B Logical Depth: 2048, Port B Logical Width: 8
--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered
V1_q_b[7]_PORT_A_data_in = BUS(R1_data[7], R1_data[2]);
V1_q_b[7]_PORT_A_data_in_reg = DFFE(V1_q_b[7]_PORT_A_data_in, V1_q_b[7]_clock_0, , , );
V1_q_b[7]_PORT_A_address = BUS(R1_cnt2[0], R1_cnt2[1], R1_cnt2[2], R1_cnt2[3], R1_cnt2[4], R1_cnt2[5], R1_cnt2[6], R1_cnt2[7], R1_cnt2[8], R1_cnt2[9], R1_cnt2[10]);
V1_q_b[7]_PORT_A_address_reg = DFFE(V1_q_b[7]_PORT_A_address, V1_q_b[7]_clock_0, , , );
V1_q_b[7]_PORT_B_address = BUS(M1_COUNTER[0], M1_COUNTER[1], M1_COUNTER[2], M1_COUNTER[3], M1_COUNTER[4], M1_COUNTER[5], M1_COUNTER[6], M1_COUNTER[7], M1_COUNTER[8], M1_COUNTER[9], M1_COUNTER[10]);
V1_q_b[7]_PORT_B_address_reg = DFFE(V1_q_b[7]_PORT_B_address, V1_q_b[7]_clock_1, , , );
V1_q_b[7]_PORT_A_write_enable = VCC;
V1_q_b[7]_PORT_A_write_enable_reg = DFFE(V1_q_b[7]_PORT_A_write_enable, V1_q_b[7]_clock_0, , , );
V1_q_b[7]_PORT_B_read_enable = VCC;
V1_q_b[7]_PORT_B_read_enable_reg = DFFE(V1_q_b[7]_PORT_B_read_enable, V1_q_b[7]_clock_1, , , );
V1_q_b[7]_clock_0 = GLOBAL(CLK);
V1_q_b[7]_clock_1 = GLOBAL(CLK);
V1_q_b[7]_PORT_B_data_out = MEMORY(V1_q_b[7]_PORT_A_data_in_reg, , V1_q_b[7]_PORT_A_address_reg, V1_q_b[7]_PORT_B_address_reg, V1_q_b[7]_PORT_A_write_enable_reg, V1_q_b[7]_PORT_B_read_enable_reg, , , V1_q_b[7]_clock_0, V1_q_b[7]_clock_1, , , , );
V1_q_b[7] = V1_q_b[7]_PORT_B_data_out[0];

--V1_q_b[2] is dram:inst|altsyncram:altsyncram_component|altsyncram_3771:auto_generated|q_b[2] at M4K_X13_Y7
V1_q_b[7]_PORT_A_data_in = BUS(R1_data[7], R1_data[2]);
V1_q_b[7]_PORT_A_data_in_reg = DFFE(V1_q_b[7]_PORT_A_data_in, V1_q_b[7]_clock_0, , , );
V1_q_b[7]_PORT_A_address = BUS(R1_cnt2[0], R1_cnt2[1], R1_cnt2[2], R1_cnt2[3], R1_cnt2[4], R1_cnt2[5], R1_cnt2[6], R1_cnt2[7], R1_cnt2[8], R1_cnt2[9], R1_cnt2[10]);
V1_q_b[7]_PORT_A_address_reg = DFFE(V1_q_b[7]_PORT_A_address, V1_q_b[7]_clock_0, , , );
V1_q_b[7]_PORT_B_address = BUS(M1_COUNTER[0], M1_COUNTER[1], M1_COUNTER[2], M1_COUNTER[3], M1_COUNTER[4], M1_COUNTER[5], M1_COUNTER[6], M1_COUNTER[7], M1_COUNTER[8], M1_COUNTER[9], M1_COUNTER[10]);
V1_q_b[7]_PORT_B_address_reg = DFFE(V1_q_b[7]_PORT_B_address, V1_q_b[7]_clock_1, , , );
V1_q_b[7]_PORT_A_write_enable = VCC;
V1_q_b[7]_PORT_A_write_enable_reg = DFFE(V1_q_b[7]_PORT_A_write_enable, V1_q_b[7]_clock_0, , , );
V1_q_b[7]_PORT_B_read_enable = VCC;
V1_q_b[7]_PORT_B_read_enable_reg = DFFE(V1_q_b[7]_PORT_B_read_enable, V1_q_b[7]_clock_1, , , );
V1_q_b[7]_clock_0 = GLOBAL(CLK);
V1_q_b[7]_clock_1 = GLOBAL(CLK);
V1_q_b[7]_PORT_B_data_out = MEMORY(V1_q_b[7]_PORT_A_data_in_reg, , V1_q_b[7]_PORT_A_address_reg, V1_q_b[7]_PORT_B_address_reg, V1_q_b[7]_PORT_A_write_enable_reg, V1_q_b[7]_PORT_B_read_enable_reg, , , V1_q_b[7]_clock_0, V1_q_b[7]_clock_1, , , , );
V1_q_b[2] = V1_q_b[7]_PORT_B_data_out[1];


--H1_RAMTMP2[7] is BUS_1:inst5|RAMTMP2[7] at LC_X18_Y2_N7
--operation mode is normal

H1_RAMTMP2[7]_lut_out = X1_q_a[6] & (H1_RAMTMP2[7] # H1L59 & A1L84) # !X1_q_a[6] & H1L59 & A1L84;
H1_RAMTMP2[7] = DFFEA(H1_RAMTMP2[7]_lut_out, !GLOBAL(CLK), VCC, , H1L92, , );


--H1_RAMTMP6[0] is BUS_1:inst5|RAMTMP6[0] at LC_X20_Y3_N6
--operation mode is normal

H1_RAMTMP6[0]_lut_out = X1_q_a[2] & (H1_RAMTMP6[0] # H1L301 & H1L601) # !X1_q_a[2] & H1L301 & H1L601;
H1_RAMTMP6[0] = DFFEA(H1_RAMTMP6[0]_lut_out, !GLOBAL(CLK), VCC, , H1L92, , );


--S1L4Q is CONV_SINGLE:inst22|CURRENT_STATE~13 at LC_X16_Y4_N9
--operation mode is normal

S1L4Q_lut_out = S1L4Q & (S1L46 # S1L3Q & S1L53) # !S1L4Q & S1L3Q & S1L53;
S1L4Q = DFFEA(S1L4Q_lut_out, GLOBAL(CLK), VCC, , , , );


--S1L46 is CONV_SINGLE:inst22|LessThan~17 at LC_X16_Y4_N7
--operation mode is normal

S1L46_carry_eqn = (!S1L25 & S1L26) # (S1L25 & S1L36);
S1L46 = S1L58 & (S1L46_carry_eqn # !N1_ADOUT_A[7]) # !S1L58 & S1L46_carry_eqn & !N1_ADOUT_A[7];


--S1L56 is CONV_SINGLE:inst22|NEXT_STATE.st0~106 at LC_X20_Y3_N7
--operation mode is normal

S1L56 = !H1_RAMTMP6[0] & (S1L5Q # !S1L1Q);


--S1L2Q is CONV_SINGLE:inst22|CURRENT_STATE~11 at LC_X16_Y3_N6
--operation mode is normal

S1L2Q_lut_out = H1_RAMTMP6[0] & (S1L07 & S1L2Q # !S1L1Q);
S1L2Q = DFFEA(S1L2Q_lut_out, GLOBAL(CLK), VCC, , , , );


--H1_RAMTMP7[1] is BUS_1:inst5|RAMTMP7[1] at LC_X16_Y1_N1
--operation mode is normal

H1_RAMTMP7[1]_lut_out = X1_q_a[3] & (H1_RAMTMP7[1] # A1L45 & H1L79) # !X1_q_a[3] & A1L45 & H1L79;
H1_RAMTMP7[1] = DFFEA(H1_RAMTMP7[1]_lut_out, !GLOBAL(CLK), VCC, , H1L92, , );


--H1_RAMTMP7[7] is BUS_1:inst5|RAMTMP7[7] at LC_X16_Y1_N9
--operation mode is normal

H1_RAMTMP7[7]_lut_out = A1L84 & (H1L79 # H1_RAMTMP7[7] & X1_q_a[3]) # !A1L84 & H1_RAMTMP7[7] & X1_q_a[3];
H1_RAMTMP7[7] = DFFEA(H1_RAMTMP7[7]_lut_out, !GLOBAL(CLK), VCC, , H1L92, , );


--N1_ADOUT_A[7] is MAX114:inst11|ADOUT_A[7] at LC_X16_Y8_N8
--operation mode is normal

N1_ADOUT_A[7]_sload_eqn = ADIN[7];
N1_ADOUT_A[7] = DFFEA(N1_ADOUT_A[7]_sload_eqn, GLOBAL(CLK), VCC, , N1L62, , );


--S1L66 is CONV_SINGLE:inst22|reduce_nor~39 at LC_X16_Y3_N2
--operation mode is normal

N1_ADOUT_A[1]_qfbk = N1_ADOUT_A[1];
S1L66 = N1_ADOUT_A[7] & (H1_RAMTMP7[1] $ N1_ADOUT_A[1]_qfbk # !H1_RAMTMP7[7]) # !N1_ADOUT_A[7] & (H1_RAMTMP7[7] # H1_RAMTMP7[1] $ N1_ADOUT_A[1]_qfbk);

--N1_ADOUT_A[1] is MAX114:inst11|ADOUT_A[1] at LC_X16_Y3_N2
--operation mode is normal

N1_ADOUT_A[1]_sload_eqn = ADIN[1];
N1_ADOUT_A[1] = DFFEA(N1_ADOUT_A[1]_sload_eqn, GLOBAL(CLK), VCC, , N1L62, , );


--H1_RAMTMP7[0] is BUS_1:inst5|RAMTMP7[0] at LC_X17_Y2_N9
--operation mode is normal

H1_RAMTMP7[0]_lut_out = X1_q_a[3] & (H1_RAMTMP7[0] # A1L55 & H1L79) # !X1_q_a[3] & A1L55 & H1L79;
H1_RAMTMP7[0] = DFFEA(H1_RAMTMP7[0]_lut_out, !GLOBAL(CLK), VCC, , H1L92, , );


--H1_RAMTMP7[5] is BUS_1:inst5|RAMTMP7[5] at LC_X16_Y1_N2
--operation mode is normal

H1_RAMTMP7[5]_lut_out = A1L05 & (H1L79 # H1_RAMTMP7[5] & X1_q_a[3]) # !A1L05 & H1_RAMTMP7[5] & X1_q_a[3];
H1_RAMTMP7[5] = DFFEA(H1_RAMTMP7[5]_lut_out, !GLOBAL(CLK), VCC, , H1L92, , );


--N1_ADOUT_A[5] is MAX114:inst11|ADOUT_A[5] at LC_X16_Y8_N9
--operation mode is normal

N1_ADOUT_A[5]_lut_out = ADIN[5];
N1_ADOUT_A[5] = DFFEA(N1_ADOUT_A[5]_lut_out, GLOBAL(CLK), VCC, , N1L62, , );


--S1L76 is CONV_SINGLE:inst22|reduce_nor~40 at LC_X16_Y3_N3
--operation mode is normal

N1_ADOUT_A[0]_qfbk = N1_ADOUT_A[0];
S1L76 = N1_ADOUT_A[5] & (H1_RAMTMP7[0] $ N1_ADOUT_A[0]_qfbk # !H1_RAMTMP7[5]) # !N1_ADOUT_A[5] & (H1_RAMTMP7[5] # H1_RAMTMP7[0] $ N1_ADOUT_A[0]_qfbk);

--N1_ADOUT_A[0] is MAX114:inst11|ADOUT_A[0] at LC_X16_Y3_N3
--operation mode is normal

N1_ADOUT_A[0]_sload_eqn = ADIN[0];
N1_ADOUT_A[0] = DFFEA(N1_ADOUT_A[0]_sload_eqn, GLOBAL(CLK), VCC, , N1L62, , );


--H1_RAMTMP7[3] is BUS_1:inst5|RAMTMP7[3] at LC_X16_Y1_N7
--operation mode is normal

H1_RAMTMP7[3]_lut_out = A1L25 & (H1L79 # H1_RAMTMP7[3] & X1_q_a[3]) # !A1L25 & H1_RAMTMP7[3] & X1_q_a[3];
H1_RAMTMP7[3] = DFFEA(H1_RAMTMP7[3]_lut_out, !GLOBAL(CLK), VCC, , H1L92, , );


--H1_RAMTMP7[4] is BUS_1:inst5|RAMTMP7[4] at LC_X16_Y1_N6
--operation mode is normal

H1_RAMTMP7[4]_lut_out = X1_q_a[3] & (H1_RAMTMP7[4] # H1L79 & A1L15) # !X1_q_a[3] & H1L79 & A1L15;
H1_RAMTMP7[4] = DFFEA(H1_RAMTMP7[4]_lut_out, !GLOBAL(CLK), VCC, , H1L92, , );


--N1_ADOUT_A[4] is MAX114:inst11|ADOUT_A[4] at LC_X16_Y8_N3
--operation mode is normal

N1_ADOUT_A[4]_lut_out = ADIN[4];
N1_ADOUT_A[4] = DFFEA(N1_ADOUT_A[4]_lut_out, GLOBAL(CLK), VCC, , N1L62, , );


--S1L86 is CONV_SINGLE:inst22|reduce_nor~41 at LC_X16_Y3_N9
--operation mode is normal

N1_ADOUT_A[3]_qfbk = N1_ADOUT_A[3];
S1L86 = N1_ADOUT_A[4] & (N1_ADOUT_A[3]_qfbk $ H1_RAMTMP7[3] # !H1_RAMTMP7[4]) # !N1_ADOUT_A[4] & (H1_RAMTMP7[4] # N1_ADOUT_A[3]_qfbk $ H1_RAMTMP7[3]);

--N1_ADOUT_A[3] is MAX114:inst11|ADOUT_A[3] at LC_X16_Y3_N9
--operation mode is normal

N1_ADOUT_A[3]_sload_eqn = ADIN[3];
N1_ADOUT_A[3] = DFFEA(N1_ADOUT_A[3]_sload_eqn, GLOBAL(CLK), VCC, , N1L62, , );


--H1_RAMTMP7[6] is BUS_1:inst5|RAMTMP7[6] at LC_X16_Y1_N0
--operation mode is normal

H1_RAMTMP7[6]_lut_out = X1_q_a[3] & (H1_RAMTMP7[6] # H1L79 & A1L94) # !X1_q_a[3] & H1L79 & A1L94;
H1_RAMTMP7[6] = DFFEA(H1_RAMTMP7[6]_lut_out, !GLOBAL(CLK), VCC, , H1L92, , );


--H1_RAMTMP7[2] is BUS_1:inst5|RAMTMP7[2] at LC_X18_Y2_N6
--operation mode is normal

H1_RAMTMP7[2]_lut_out = A1L35 & (H1L79 # X1_q_a[3] & H1_RAMTMP7[2]) # !A1L35 & X1_q_a[3] & H1_RAMTMP7[2];
H1_RAMTMP7[2] = DFFEA(H1_RAMTMP7[2]_lut_out, !GLOBAL(CLK), VCC, , H1L92, , );


--N1_ADOUT_A[2] is MAX114:inst11|ADOUT_A[2] at LC_X18_Y2_N2
--operation mode is normal

N1_ADOUT_A[2]_sload_eqn = ADIN[2];
N1_ADOUT_A[2] = DFFEA(N1_ADOUT_A[2]_sload_eqn, GLOBAL(CLK), VCC, , N1L62, , );


--S1L96 is CONV_SINGLE:inst22|reduce_nor~42 at LC_X18_Y2_N3
--operation mode is normal

N1_ADOUT_A[6]_qfbk = N1_ADOUT_A[6];
S1L96 = N1_ADOUT_A[2] & (H1_RAMTMP7[6] $ N1_ADOUT_A[6]_qfbk # !H1_RAMTMP7[2]) # !N1_ADOUT_A[2] & (H1_RAMTMP7[2] # H1_RAMTMP7[6] $ N1_ADOUT_A[6]_qfbk);

--N1_ADOUT_A[6] is MAX114:inst11|ADOUT_A[6] at LC_X18_Y2_N3
--operation mode is normal

N1_ADOUT_A[6]_sload_eqn = ADIN[6];
N1_ADOUT_A[6] = DFFEA(N1_ADOUT_A[6]_sload_eqn, GLOBAL(CLK), VCC, , N1L62, , );


--S1L07 is CONV_SINGLE:inst22|reduce_nor~43 at LC_X16_Y3_N7
--operation mode is normal

S1L07 = S1L86 # S1L96 # S1L66 # S1L76;


--L1L44 is VOLTAGE_CONV:inst9|LessThan~7COUT0 at LC_X19_Y4_N6
--operation mode is arithmetic

L1L44_cout_0 = L1L51 & V1_q_b[6] & !L1L04 # !L1L51 & (V1_q_b[6] # !L1L04);
L1L44 = CARRY(L1L44_cout_0);

--L1L54 is VOLTAGE_CONV:inst9|LessThan~7COUT1 at LC_X19_Y4_N6
--operation mode is arithmetic

L1L54_cout_1 = L1L51 & V1_q_b[6] & !L1L14 # !L1L51 & (V1_q_b[6] # !L1L14);
L1L54 = CARRY(L1L54_cout_1);


--V2_q_b[7] is dram:inst14|altsyncram:altsyncram_component|altsyncram_3771:auto_generated|q_b[7] at M4K_X13_Y5
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 2048, Port A Width: 2, Port B Depth: 2048, Port B Width: 2
--Port A Logical Depth: 2048, Port A Logical Width: 8, Port B Logical Depth: 2048, Port B Logical Width: 8
--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered
V2_q_b[7]_PORT_A_data_in = BUS(R2_data[7], R2_data[4]);
V2_q_b[7]_PORT_A_data_in_reg = DFFE(V2_q_b[7]_PORT_A_data_in, V2_q_b[7]_clock_0, , , );
V2_q_b[7]_PORT_A_address = BUS(R2_cnt2[0], R2_cnt2[1], R2_cnt2[2], R2_cnt2[3], R2_cnt2[4], R2_cnt2[5], R2_cnt2[6], R2_cnt2[7], R2_cnt2[8], R2_cnt2[9], R2_cnt2[10]);
V2_q_b[7]_PORT_A_address_reg = DFFE(V2_q_b[7]_PORT_A_address, V2_q_b[7]_clock_0, , , );
V2_q_b[7]_PORT_B_address = BUS(M1_COUNTER[0], M1_COUNTER[1], M1_COUNTER[2], M1_COUNTER[3], M1_COUNTER[4], M1_COUNTER[5], M1_COUNTER[6], M1_COUNTER[7], M1_COUNTER[8], M1_COUNTER[9], M1_COUNTER[10]);
V2_q_b[7]_PORT_B_address_reg = DFFE(V2_q_b[7]_PORT_B_address, V2_q_b[7]_clock_1, , , );
V2_q_b[7]_PORT_A_write_enable = VCC;
V2_q_b[7]_PORT_A_write_enable_reg = DFFE(V2_q_b[7]_PORT_A_write_enable, V2_q_b[7]_clock_0, , , );
V2_q_b[7]_PORT_B_read_enable = VCC;
V2_q_b[7]_PORT_B_read_enable_reg = DFFE(V2_q_b[7]_PORT_B_read_enable, V2_q_b[7]_clock_1, , , );
V2_q_b[7]_clock_0 = GLOBAL(CLK);
V2_q_b[7]_clock_1 = GLOBAL(CLK);
V2_q_b[7]_PORT_B_data_out = MEMORY(V2_q_b[7]_PORT_A_data_in_reg, , V2_q_b[7]_PORT_A_address_reg, V2_q_b[7]_PORT_B_address_reg, V2_q_b[7]_PORT_A_write_enable_reg, V2_q_b[7]_PORT_B_read_enable_reg, , , V2_q_b[7]_clock_0, V2_q_b[7]_clock_1, , , , );
V2_q_b[7] = V2_q_b[7]_PORT_B_data_out[0];

--V2_q_b[4] is dram:inst14|altsyncram:altsyncram_component|altsyncram_3771:auto_generated|q_b[4] at M4K_X13_Y5
V2_q_b[7]_PORT_A_data_in = BUS(R2_data[7], R2_data[4]);
V2_q_b[7]_PORT_A_data_in_reg = DFFE(V2_q_b[7]_PORT_A_data_in, V2_q_b[7]_clock_0, , , );
V2_q_b[7]_PORT_A_address = BUS(R2_cnt2[0], R2_cnt2[1], R2_cnt2[2], R2_cnt2[3], R2_cnt2[4], R2_cnt2[5], R2_cnt2[6], R2_cnt2[7], R2_cnt2[8], R2_cnt2[9], R2_cnt2[10]);
V2_q_b[7]_PORT_A_address_reg = DFFE(V2_q_b[7]_PORT_A_address, V2_q_b[7]_clock_0, , , );
V2_q_b[7]_PORT_B_address = BUS(M1_COUNTER[0], M1_COUNTER[1], M1_COUNTER[2], M1_COUNTER[3], M1_COUNTER[4], M1_COUNTER[5], M1_COUNTER[6], M1_COUNTER[7], M1_COUNTER[8], M1_COUNTER[9], M1_COUNTER[10]);
V2_q_b[7]_PORT_B_address_reg = DFFE(V2_q_b[7]_PORT_B_address, V2_q_b[7]_clock_1, , , );
V2_q_b[7]_PORT_A_write_enable = VCC;
V2_q_b[7]_PORT_A_write_enable_reg = DFFE(V2_q_b[7]_PORT_A_write_enable, V2_q_b[7]_clock_0, , , );
V2_q_b[7]_PORT_B_read_enable = VCC;
V2_q_b[7]_PORT_B_read_enable_reg = DFFE(V2_q_b[7]_PORT_B_read_enable, V2_q_b[7]_clock_1, , , );
V2_q_b[7]_clock_0 = GLOBAL(CLK);
V2_q_b[7]_clock_1 = GLOBAL(CLK);
V2_q_b[7]_PORT_B_data_out = MEMORY(V2_q_b[7]_PORT_A_data_in_reg, , V2_q_b[7]_PORT_A_address_reg, V2_q_b[7]_PORT_B_address_reg, V2_q_b[7]_PORT_A_write_enable_reg, V2_q_b[7]_PORT_B_read_enable_reg, , , V2_q_b[7]_clock_0, V2_q_b[7]_clock_1, , , , );