scanwave.fit.eqn

数字示波器的FPGA实现 VHDL编写 Quartus7.1测试通过

L2L71_carry_eqn = (!L2L01 & L2L56) # (L2L01 & L2L66);
L2L71 = H1_RAMTMP5[7] $ L2L71_carry_eqn $ V2_q_b[7];

--L2_TEMP[7] is VOLTAGE_CONV:inst17|TEMP[7] at LC_X18_Y3_N7
--operation mode is normal

L2_TEMP[7] = DFFEA(L2L71, !GLOBAL(P1_CLK), !GLOBAL(S1_EN), , !L2L64, , );


--L2L64 is VOLTAGE_CONV:inst17|LessThan~8 at LC_X19_Y3_N7
--operation mode is normal

L2L64_carry_eqn = (!L2L43 & L2L44) # (L2L43 & L2L54);
L2L64 = V2_q_b[7] & (L2L64_carry_eqn # !L2L71) # !V2_q_b[7] & L2L64_carry_eqn & !L2L71;


--H1_LATCH_ADDRES[5] is BUS_1:inst5|LATCH_ADDRES[5] at LC_X11_Y2_N3
--operation mode is normal

H1_LATCH_ADDRES[5]_lut_out = A1L05;
H1_LATCH_ADDRES[5] = DFFEA(H1_LATCH_ADDRES[5]_lut_out, !GLOBAL(ALE), VCC, , , , );


--H1_LATCH_ADDRES[4] is BUS_1:inst5|LATCH_ADDRES[4] at LC_X11_Y2_N0
--operation mode is normal

H1_LATCH_ADDRES[4]_sload_eqn = A1L15;
H1_LATCH_ADDRES[4] = DFFEA(H1_LATCH_ADDRES[4]_sload_eqn, !GLOBAL(ALE), VCC, , , , );


--H1_LATCH_ADDRES[7] is BUS_1:inst5|LATCH_ADDRES[7] at LC_X11_Y2_N2
--operation mode is normal

H1_LATCH_ADDRES[7]_lut_out = A1L84;
H1_LATCH_ADDRES[7] = DFFEA(H1_LATCH_ADDRES[7]_lut_out, !GLOBAL(ALE), VCC, , , , );


--H1L99 is BUS_1:inst5|reduce_nor~158 at LC_X11_Y2_N5
--operation mode is normal

H1_LATCH_ADDRES[6]_qfbk = H1_LATCH_ADDRES[6];
H1L99 = H1_LATCH_ADDRES[7] & H1_LATCH_ADDRES[4] & H1_LATCH_ADDRES[6]_qfbk & H1_LATCH_ADDRES[5];

--H1_LATCH_ADDRES[6] is BUS_1:inst5|LATCH_ADDRES[6] at LC_X11_Y2_N5
--operation mode is normal

H1_LATCH_ADDRES[6]_sload_eqn = A1L94;
H1_LATCH_ADDRES[6] = DFFEA(H1_LATCH_ADDRES[6]_sload_eqn, !GLOBAL(ALE), VCC, , , , );


--H1L001 is BUS_1:inst5|reduce_nor~159 at LC_X20_Y3_N3
--operation mode is normal

H1_LATCH_ADDRES[1]_qfbk = H1_LATCH_ADDRES[1];
H1L001 = !H1_LATCH_ADDRES[2] & H1_LATCH_ADDRES[1]_qfbk & H1L99;

--H1_LATCH_ADDRES[1] is BUS_1:inst5|LATCH_ADDRES[1] at LC_X20_Y3_N3
--operation mode is normal

H1_LATCH_ADDRES[1]_sload_eqn = A1L45;
H1_LATCH_ADDRES[1] = DFFEA(H1_LATCH_ADDRES[1]_sload_eqn, !GLOBAL(ALE), VCC, , , , );


--H1L49 is BUS_1:inst5|reduce_nor~3 at LC_X20_Y3_N1
--operation mode is normal

H1_LATCH_ADDRES[0]_qfbk = H1_LATCH_ADDRES[0];
H1L49 = H1L001 & H1_LATCH_ADDRES[0]_qfbk & !H1_LATCH_ADDRES[3];

--H1_LATCH_ADDRES[0] is BUS_1:inst5|LATCH_ADDRES[0] at LC_X20_Y3_N1
--operation mode is normal

H1_LATCH_ADDRES[0]_sload_eqn = A1L55;
H1_LATCH_ADDRES[0] = DFFEA(H1_LATCH_ADDRES[0]_sload_eqn, !GLOBAL(ALE), VCC, , , , );


--X1_q_a[1] is BUS_1:inst5|altsyncram:reduce_or_rtl_1|altsyncram_ccj:auto_generated|q_a[1] at M4K_X13_Y1
--RAM Block Operation Mode: ROM
--Port A Depth: 256, Port A Width: 8
--Port A Logical Depth: 256, Port A Logical Width: 8
--Port A Input: Registered, Port A Output: Un-registered
X1_q_a[1]_PORT_A_address = BUS(A1L94, A1L05, A1L15, A1L25, A1L35, A1L45, A1L55, A1L84);
X1_q_a[1]_PORT_A_address_reg = DFFE(X1_q_a[1]_PORT_A_address, X1_q_a[1]_clock_0, , , );
X1_q_a[1]_clock_0 = !GLOBAL(ALE);
X1_q_a[1]_PORT_A_data_out = MEMORY(, , X1_q_a[1]_PORT_A_address_reg, , , , , , X1_q_a[1]_clock_0, , , , , );
X1_q_a[1] = X1_q_a[1]_PORT_A_data_out[0];

--X1_q_a[7] is BUS_1:inst5|altsyncram:reduce_or_rtl_1|altsyncram_ccj:auto_generated|q_a[7] at M4K_X13_Y1
X1_q_a[1]_PORT_A_address = BUS(A1L94, A1L05, A1L15, A1L25, A1L35, A1L45, A1L55, A1L84);
X1_q_a[1]_PORT_A_address_reg = DFFE(X1_q_a[1]_PORT_A_address, X1_q_a[1]_clock_0, , , );
X1_q_a[1]_clock_0 = !GLOBAL(ALE);
X1_q_a[1]_PORT_A_data_out = MEMORY(, , X1_q_a[1]_PORT_A_address_reg, , , , , , X1_q_a[1]_clock_0, , , , , );
X1_q_a[7] = X1_q_a[1]_PORT_A_data_out[7];

--X1_q_a[4] is BUS_1:inst5|altsyncram:reduce_or_rtl_1|altsyncram_ccj:auto_generated|q_a[4] at M4K_X13_Y1
X1_q_a[1]_PORT_A_address = BUS(A1L94, A1L05, A1L15, A1L25, A1L35, A1L45, A1L55, A1L84);
X1_q_a[1]_PORT_A_address_reg = DFFE(X1_q_a[1]_PORT_A_address, X1_q_a[1]_clock_0, , , );
X1_q_a[1]_clock_0 = !GLOBAL(ALE);
X1_q_a[1]_PORT_A_data_out = MEMORY(, , X1_q_a[1]_PORT_A_address_reg, , , , , , X1_q_a[1]_clock_0, , , , , );
X1_q_a[4] = X1_q_a[1]_PORT_A_data_out[6];

--X1_q_a[5] is BUS_1:inst5|altsyncram:reduce_or_rtl_1|altsyncram_ccj:auto_generated|q_a[5] at M4K_X13_Y1
X1_q_a[1]_PORT_A_address = BUS(A1L94, A1L05, A1L15, A1L25, A1L35, A1L45, A1L55, A1L84);
X1_q_a[1]_PORT_A_address_reg = DFFE(X1_q_a[1]_PORT_A_address, X1_q_a[1]_clock_0, , , );
X1_q_a[1]_clock_0 = !GLOBAL(ALE);
X1_q_a[1]_PORT_A_data_out = MEMORY(, , X1_q_a[1]_PORT_A_address_reg, , , , , , X1_q_a[1]_clock_0, , , , , );
X1_q_a[5] = X1_q_a[1]_PORT_A_data_out[5];

--X1_q_a[3] is BUS_1:inst5|altsyncram:reduce_or_rtl_1|altsyncram_ccj:auto_generated|q_a[3] at M4K_X13_Y1
X1_q_a[1]_PORT_A_address = BUS(A1L94, A1L05, A1L15, A1L25, A1L35, A1L45, A1L55, A1L84);
X1_q_a[1]_PORT_A_address_reg = DFFE(X1_q_a[1]_PORT_A_address, X1_q_a[1]_clock_0, , , );
X1_q_a[1]_clock_0 = !GLOBAL(ALE);
X1_q_a[1]_PORT_A_data_out = MEMORY(, , X1_q_a[1]_PORT_A_address_reg, , , , , , X1_q_a[1]_clock_0, , , , , );
X1_q_a[3] = X1_q_a[1]_PORT_A_data_out[4];

--X1_q_a[2] is BUS_1:inst5|altsyncram:reduce_or_rtl_1|altsyncram_ccj:auto_generated|q_a[2] at M4K_X13_Y1
X1_q_a[1]_PORT_A_address = BUS(A1L94, A1L05, A1L15, A1L25, A1L35, A1L45, A1L55, A1L84);
X1_q_a[1]_PORT_A_address_reg = DFFE(X1_q_a[1]_PORT_A_address, X1_q_a[1]_clock_0, , , );
X1_q_a[1]_clock_0 = !GLOBAL(ALE);
X1_q_a[1]_PORT_A_data_out = MEMORY(, , X1_q_a[1]_PORT_A_address_reg, , , , , , X1_q_a[1]_clock_0, , , , , );
X1_q_a[2] = X1_q_a[1]_PORT_A_data_out[3];

--X1_q_a[6] is BUS_1:inst5|altsyncram:reduce_or_rtl_1|altsyncram_ccj:auto_generated|q_a[6] at M4K_X13_Y1
X1_q_a[1]_PORT_A_address = BUS(A1L94, A1L05, A1L15, A1L25, A1L35, A1L45, A1L55, A1L84);
X1_q_a[1]_PORT_A_address_reg = DFFE(X1_q_a[1]_PORT_A_address, X1_q_a[1]_clock_0, , , );
X1_q_a[1]_clock_0 = !GLOBAL(ALE);
X1_q_a[1]_PORT_A_data_out = MEMORY(, , X1_q_a[1]_PORT_A_address_reg, , , , , , X1_q_a[1]_clock_0, , , , , );
X1_q_a[6] = X1_q_a[1]_PORT_A_data_out[2];

--X1_q_a[0] is BUS_1:inst5|altsyncram:reduce_or_rtl_1|altsyncram_ccj:auto_generated|q_a[0] at M4K_X13_Y1
X1_q_a[1]_PORT_A_address = BUS(A1L94, A1L05, A1L15, A1L25, A1L35, A1L45, A1L55, A1L84);
X1_q_a[1]_PORT_A_address_reg = DFFE(X1_q_a[1]_PORT_A_address, X1_q_a[1]_clock_0, , , );
X1_q_a[1]_clock_0 = !GLOBAL(ALE);
X1_q_a[1]_PORT_A_data_out = MEMORY(, , X1_q_a[1]_PORT_A_address_reg, , , , , , X1_q_a[1]_clock_0, , , , , );
X1_q_a[0] = X1_q_a[1]_PORT_A_data_out[1];


--H1L92 is BUS_1:inst5|process2~0 at LC_X11_Y2_N9
--operation mode is normal

H1L92 = !WR & !CS;


--G1L16 is generator_accB:inst4|add~18 at LC_X10_Y1_N1
--operation mode is arithmetic

G1L16_carry_eqn = (!G1L65 & G1L95) # (G1L65 & G1L06);
G1L16 = G1_REG_Q[17] $ G1L16_carry_eqn;

--G1L36 is generator_accB:inst4|add~18COUT0 at LC_X10_Y1_N1
--operation mode is arithmetic

G1L36_cout_0 = !G1L95 # !G1_REG_Q[17];
G1L36 = CARRY(G1L36_cout_0);

--G1L46 is generator_accB:inst4|add~18COUT1 at LC_X10_Y1_N1
--operation mode is arithmetic

G1L46_cout_1 = !G1L06 # !G1_REG_Q[17];
G1L46 = CARRY(G1L46_cout_1);


--G1L56 is generator_accB:inst4|add~19 at LC_X10_Y1_N2
--operation mode is arithmetic

G1L56_carry_eqn = (!G1L65 & G1L36) # (G1L65 & G1L46);
G1L56 = G1_REG_Q[18] $ !G1L56_carry_eqn;

--G1L76 is generator_accB:inst4|add~19COUT0 at LC_X10_Y1_N2
--operation mode is arithmetic

G1L76_cout_0 = G1_REG_Q[18] & !G1L36;
G1L76 = CARRY(G1L76_cout_0);

--G1L86 is generator_accB:inst4|add~19COUT1 at LC_X10_Y1_N2
--operation mode is arithmetic

G1L86_cout_1 = G1_REG_Q[18] & !G1L46;
G1L86 = CARRY(G1L86_cout_1);


--G1L96 is generator_accB:inst4|add~20 at LC_X10_Y1_N3
--operation mode is arithmetic

G1L96_carry_eqn = (!G1L65 & G1L76) # (G1L65 & G1L86);
G1L96 = G1_REG_Q[19] $ G1L96_carry_eqn;

--G1L17 is generator_accB:inst4|add~20COUT0 at LC_X10_Y1_N3
--operation mode is arithmetic

G1L17_cout_0 = !G1L76 # !G1_REG_Q[19];
G1L17 = CARRY(G1L17_cout_0);

--G1L27 is generator_accB:inst4|add~20COUT1 at LC_X10_Y1_N3
--operation mode is arithmetic

G1L27_cout_1 = !G1L86 # !G1_REG_Q[19];
G1L27 = CARRY(G1L27_cout_1);


--G1L99 is generator_accB:inst4|REG_Q~538 at LC_X10_Y1_N7
--operation mode is normal

G1L99 = !G1L96 & !G1L56 & !G1L16;


--G1L37 is generator_accB:inst4|add~21 at LC_X10_Y1_N4
--operation mode is arithmetic

G1L37_carry_eqn = (!G1L65 & G1L17) # (G1L65 & G1L27);
G1L37 = G1_REG_Q[20] $ !G1L37_carry_eqn;

--G1L47 is generator_accB:inst4|add~21COUT at LC_X10_Y1_N4
--operation mode is arithmetic

G1L47 = CARRY(G1_REG_Q[20] & !G1L27);


--G1L57 is generator_accB:inst4|add~22 at LC_X10_Y1_N5
--operation mode is normal

G1L57_carry_eqn = G1L47;
G1L57 = G1L57_carry_eqn $ G1_REG_Q[21];


--G1L201 is generator_accB:inst4|TEMP~0 at LC_X10_Y1_N6
--operation mode is normal

G1L201 = !H1_TMP & G1L37 & !G1L99 & G1L57;


--L1L51 is VOLTAGE_CONV:inst9|add~7 at LC_X18_Y4_N6
--operation mode is arithmetic

L1L51_carry_eqn = (!L1L01 & L1L26) # (L1L01 & L1L36);
L1L51 = V1_q_b[6] $ H1_RAMTMP2[6] $ !L1L51_carry_eqn;

--L1_TEMP[6] is VOLTAGE_CONV:inst9|TEMP[6] at LC_X18_Y4_N6
--operation mode is arithmetic

L1_TEMP[6] = DFFEA(L1L51, !GLOBAL(P1_CLK), !GLOBAL(S1_EN), , !L1L64, , );

--L1L56 is VOLTAGE_CONV:inst9|TEMP[6]~COUT0 at LC_X18_Y4_N6
--operation mode is arithmetic

L1L56_cout_0 = V1_q_b[6] & (H1_RAMTMP2[6] # !L1L26) # !V1_q_b[6] & H1_RAMTMP2[6] & !L1L26;
L1L56 = CARRY(L1L56_cout_0);

--L1L66 is VOLTAGE_CONV:inst9|TEMP[6]~COUT1 at LC_X18_Y4_N6
--operation mode is arithmetic

L1L66_cout_1 = V1_q_b[6] & (H1_RAMTMP2[6] # !L1L36) # !V1_q_b[6] & H1_RAMTMP2[6] & !L1L36;
L1L66 = CARRY(L1L66_cout_1);


--L2L51 is VOLTAGE_CONV:inst17|add~7 at LC_X18_Y3_N6
--operation mode is arithmetic

L2L51_carry_eqn = (!L2L01 & L2L26) # (L2L01 & L2L36);
L2L51 = H1_RAMTMP5[6] $ V2_q_b[6] $ !L2L51_carry_eqn;

--L2_TEMP[6] is VOLTAGE_CONV:inst17|TEMP[6] at LC_X18_Y3_N6
--operation mode is arithmetic

L2_TEMP[6] = DFFEA(L2L51, !GLOBAL(P1_CLK), !GLOBAL(S1_EN), , !L2L64, , );

--L2L56 is VOLTAGE_CONV:inst17|TEMP[6]~COUT0 at LC_X18_Y3_N6
--operation mode is arithmetic

L2L56_cout_0 = H1_RAMTMP5[6] & (V2_q_b[6] # !L2L26) # !H1_RAMTMP5[6] & V2_q_b[6] & !L2L26;
L2L56 = CARRY(L2L56_cout_0);

--L2L66 is VOLTAGE_CONV:inst17|TEMP[6]~COUT1 at LC_X18_Y3_N6
--operation mode is arithmetic

L2L66_cout_1 = H1_RAMTMP5[6] & (V2_q_b[6] # !L2L36) # !H1_RAMTMP5[6] & V2_q_b[6] & !L2L36;
L2L66 = CARRY(L2L66_cout_1);


--L1L31 is VOLTAGE_CONV:inst9|add~6 at LC_X18_Y4_N5
--operation mode is arithmetic

L1L31_carry_eqn = (!L1L01 & GND) # (L1L01 & VCC);
L1L31 = H1_RAMTMP2[5] $ V1_q_b[5] $ L1L31_carry_eqn;

--L1_TEMP[5] is VOLTAGE_CONV:inst9|TEMP[5] at LC_X18_Y4_N5
--operation mode is arithmetic

L1_TEMP[5] = DFFEA(L1L31, !GLOBAL(P1_CLK), !GLOBAL(S1_EN), , !L1L64, , );

--L1L26 is VOLTAGE_CONV:inst9|TEMP[5]~COUT0 at LC_X18_Y4_N5
--operation mode is arithmetic

L1L26_cout_0 = H1_RAMTMP2[5] & !V1_q_b[5] & !L1L01 # !H1_RAMTMP2[5] & (!L1L01 # !V1_q_b[5]);
L1L26 = CARRY(L1L26_cout_0);

--L1L36 is VOLTAGE_CONV:inst9|TEMP[5]~COUT1 at LC_X18_Y4_N5
--operation mode is arithmetic

L1L36_cout_1 = H1_RAMTMP2[5] & !V1_q_b[5] & !L1L01 # !H1_RAMTMP2[5] & (!L1L01 # !V1_q_b[5]);
L1L36 = CARRY(L1L36_cout_1);


--L2L31 is VOLTAGE_CONV:inst17|add~6 at LC_X18_Y3_N5