scanwave.fit.eqn

数字示波器的FPGA实现 VHDL编写 Quartus7.1测试通过

--N1_RD is MAX114:inst11|RD at LC_X11_Y6_N4
--operation mode is normal

N1_RD_lut_out = !N1_cnt[2] & !N1_cnt[0] & !N1_cnt[1];
N1_RD = DFFEA(N1_RD_lut_out, GLOBAL(CLK), VCC, , N1L82, , );


--N1_B is MAX114:inst11|B at LC_X10_Y5_N4
--operation mode is normal

N1_B_lut_out = N1_cnt[3] & !N1_cnt[2] & N1_cnt[1] & !N1_cnt[0];
N1_B = DFFEA(N1_B_lut_out, GLOBAL(CLK), VCC, , N1L92, , );


--B1_TEMP_Q_1[7] is generator_reg81:79|TEMP_Q_1[7] at LC_X8_Y3_N9
--operation mode is normal

B1_TEMP_Q_1[7]_sload_eqn = G1_REG_Q[21];
B1_TEMP_Q_1[7] = DFFEA(B1_TEMP_Q_1[7]_sload_eqn, GLOBAL(K1_CLK), !H1_TMP, , , , );


--B1_TEMP_Q_1[6] is generator_reg81:79|TEMP_Q_1[6] at LC_X9_Y1_N5
--operation mode is normal

B1_TEMP_Q_1[6]_sload_eqn = G1_REG_Q[20];
B1_TEMP_Q_1[6] = DFFEA(B1_TEMP_Q_1[6]_sload_eqn, GLOBAL(K1_CLK), !H1_TMP, , , , );


--B1_TEMP_Q_1[5] is generator_reg81:79|TEMP_Q_1[5] at LC_X9_Y1_N0
--operation mode is normal

B1_TEMP_Q_1[5]_lut_out = G1_REG_Q[19];
B1_TEMP_Q_1[5] = DFFEA(B1_TEMP_Q_1[5]_lut_out, GLOBAL(K1_CLK), !H1_TMP, , , , );


--B1_TEMP_Q_1[4] is generator_reg81:79|TEMP_Q_1[4] at LC_X9_Y1_N3
--operation mode is normal

B1_TEMP_Q_1[4]_sload_eqn = G1_REG_Q[18];
B1_TEMP_Q_1[4] = DFFEA(B1_TEMP_Q_1[4]_sload_eqn, GLOBAL(K1_CLK), !H1_TMP, , , , );


--B1_TEMP_Q_1[3] is generator_reg81:79|TEMP_Q_1[3] at LC_X9_Y1_N2
--operation mode is normal

B1_TEMP_Q_1[3]_lut_out = G1_REG_Q[17];
B1_TEMP_Q_1[3] = DFFEA(B1_TEMP_Q_1[3]_lut_out, GLOBAL(K1_CLK), !H1_TMP, , , , );


--B1_TEMP_Q_1[2] is generator_reg81:79|TEMP_Q_1[2] at LC_X9_Y1_N8
--operation mode is normal

B1_TEMP_Q_1[2]_sload_eqn = G1_REG_Q[16];
B1_TEMP_Q_1[2] = DFFEA(B1_TEMP_Q_1[2]_sload_eqn, GLOBAL(K1_CLK), !H1_TMP, , , , );


--B1_TEMP_Q_1[1] is generator_reg81:79|TEMP_Q_1[1] at LC_X8_Y3_N0
--operation mode is normal

B1_TEMP_Q_1[1]_lut_out = G1_REG_Q[15];
B1_TEMP_Q_1[1] = DFFEA(B1_TEMP_Q_1[1]_lut_out, GLOBAL(K1_CLK), !H1_TMP, , , , );


--B1_TEMP_Q_1[0] is generator_reg81:79|TEMP_Q_1[0] at LC_X9_Y3_N3
--operation mode is normal

B1_TEMP_Q_1[0]_sload_eqn = G1_REG_Q[14];
B1_TEMP_Q_1[0] = DFFEA(B1_TEMP_Q_1[0]_sload_eqn, GLOBAL(K1_CLK), !H1_TMP, , , , );


--H1_RAMTMP0[0] is BUS_1:inst5|RAMTMP0[0] at LC_X20_Y3_N4
--operation mode is normal

H1_RAMTMP0[0]_lut_out = A1L55 & (H1L49 # H1_RAMTMP0[0] & X1_q_a[1]) # !A1L55 & H1_RAMTMP0[0] & X1_q_a[1];
H1_RAMTMP0[0] = DFFEA(H1_RAMTMP0[0]_lut_out, !GLOBAL(CLK), VCC, , H1L92, , );


--G1_TEMP is generator_accB:inst4|TEMP at LC_X10_Y1_N9
--operation mode is normal

G1_TEMP_lut_out = !G1_TEMP;
G1_TEMP = DFFEA(G1_TEMP_lut_out, GLOBAL(K1_CLK), VCC, , G1L201, , );


--H1_RAMTMP0[1] is BUS_1:inst5|RAMTMP0[1] at LC_X20_Y3_N0
--operation mode is normal

H1_RAMTMP0[1]_lut_out = H1L49 & (A1L45 # X1_q_a[1] & H1_RAMTMP0[1]) # !H1L49 & X1_q_a[1] & H1_RAMTMP0[1];
H1_RAMTMP0[1] = DFFEA(H1_RAMTMP0[1]_lut_out, !GLOBAL(CLK), VCC, , H1L92, , );


--F1L8 is MUX2_3:inst3|Q[7]~516 at LC_X20_Y3_N8
--operation mode is normal

F1L8 = H1_RAMTMP0[0] & (G1_TEMP # !H1_RAMTMP0[1]);


--F1L9 is MUX2_3:inst3|Q[7]~517 at LC_X18_Y1_N6
--operation mode is normal

F1L9 = L2_TEMP[7] & (L1_TEMP[7] # !F1L8) # !L2_TEMP[7] & F1L8 & L1_TEMP[7];


--F1L7 is MUX2_3:inst3|Q[6]~518 at LC_X18_Y1_N8
--operation mode is normal

F1L7 = L2_TEMP[6] & (L1_TEMP[6] # !F1L8) # !L2_TEMP[6] & F1L8 & L1_TEMP[6];


--F1L6 is MUX2_3:inst3|Q[5]~519 at LC_X18_Y1_N9
--operation mode is normal

F1L6 = L2_TEMP[5] & (L1_TEMP[5] # !F1L8) # !L2_TEMP[5] & F1L8 & L1_TEMP[5];


--F1L5 is MUX2_3:inst3|Q[4]~520 at LC_X18_Y1_N4
--operation mode is normal

F1L5 = L2_TEMP[4] & (L1_TEMP[4] # !F1L8) # !L2_TEMP[4] & L1_TEMP[4] & F1L8;


--F1L4 is MUX2_3:inst3|Q[3]~521 at LC_X18_Y1_N3
--operation mode is normal

F1L4 = L2_TEMP[3] & (L1_TEMP[3] # !F1L8) # !L2_TEMP[3] & F1L8 & L1_TEMP[3];


--F1L3 is MUX2_3:inst3|Q[2]~522 at LC_X18_Y1_N2
--operation mode is normal

F1L3 = F1L8 & L1_TEMP[2] # !F1L8 & L2_TEMP[2];


--F1L2 is MUX2_3:inst3|Q[1]~523 at LC_X18_Y1_N5
--operation mode is normal

F1L2 = L2_TEMP[1] & (L1_TEMP[1] # !F1L8) # !L2_TEMP[1] & F1L8 & L1_TEMP[1];


--F1L1 is MUX2_3:inst3|Q[0]~524 at LC_X18_Y1_N7
--operation mode is normal

F1L1 = L2_TEMP[0] & (L1_TEMP[0] # !F1L8) # !L2_TEMP[0] & F1L8 & L1_TEMP[0];


--N1_cnt[1] is MAX114:inst11|cnt[1] at LC_X9_Y6_N0
--operation mode is normal

N1_cnt[1]_lut_out = N1_cnt[1] & !N1_cnt[0] # !N1_cnt[1] & N1_cnt[0] & (INTN # N1_cnt[2]);
N1_cnt[1] = DFFEA(N1_cnt[1]_lut_out, GLOBAL(CLK), VCC, , , , );


--N1_cnt[2] is MAX114:inst11|cnt[2] at LC_X9_Y6_N2
--operation mode is normal

N1_cnt[2]_lut_out = !N1_cnt[2];
N1_cnt[2] = DFFEA(N1_cnt[2]_lut_out, GLOBAL(CLK), VCC, , N1L1, , );


--N1_cnt[0] is MAX114:inst11|cnt[0] at LC_X9_Y6_N3
--operation mode is normal

N1_cnt[0]_lut_out = INTN & !N1_cnt[0] & (N1_cnt[2] # !N1_cnt[1]) # !INTN & (!N1_cnt[1] & !N1_cnt[2] # !N1_cnt[0]);
N1_cnt[0] = DFFEA(N1_cnt[0]_lut_out, GLOBAL(CLK), VCC, , , , );


--N1L82 is MAX114:inst11|Mux~318 at LC_X9_Y6_N4
--operation mode is normal

N1L82 = !N1_cnt[2] & !N1_cnt[0];


--N1_cnt[3] is MAX114:inst11|cnt[3] at LC_X10_Y5_N2
--operation mode is normal

N1_cnt[3]_lut_out = !N1_cnt[3];
N1_cnt[3] = DFFEA(N1_cnt[3]_lut_out, GLOBAL(CLK), VCC, , N1L03, , );


--N1L92 is MAX114:inst11|Mux~319 at LC_X9_Y6_N9
--operation mode is normal

N1L92 = N1_cnt[1] & !N1_cnt[2] & !N1_cnt[0];


--G1_REG_Q[21] is generator_accB:inst4|REG_Q[21] at LC_X8_Y3_N2
--operation mode is normal

G1_REG_Q[21]_lut_out = G1L57 & (G1L99 # !G1L37);
G1_REG_Q[21] = DFFEA(G1_REG_Q[21]_lut_out, GLOBAL(K1_CLK), !H1_TMP, , , , );


--K1_CLK is FREDEVIDER8:inst8|CLK at LC_X8_Y6_N2
--operation mode is normal

K1_CLK_lut_out = !K1_CLK;
K1_CLK = DFFEA(K1_CLK_lut_out, GLOBAL(CLK), VCC, , K1L6, , );


--H1_TMP is BUS_1:inst5|TMP at LC_X9_Y1_N1
--operation mode is normal

H1_TMP_lut_out = H1L101 & (H1_LATCH_ADDRES[1] # X1_q_a[0] & H1_TMP) # !H1L101 & X1_q_a[0] & H1_TMP;
H1_TMP = DFFEA(H1_TMP_lut_out, !GLOBAL(CLK), VCC, , H1L92, , );


--G1_REG_Q[20] is generator_accB:inst4|REG_Q[20] at LC_X9_Y1_N9
--operation mode is normal

G1_REG_Q[20]_lut_out = G1L37 & (G1L99 # !G1L57);
G1_REG_Q[20] = DFFEA(G1_REG_Q[20]_lut_out, GLOBAL(K1_CLK), !H1_TMP, , , , );


--G1_REG_Q[19] is generator_accB:inst4|REG_Q[19] at LC_X9_Y1_N6
--operation mode is normal

G1_REG_Q[19]_lut_out = G1L96 & (G1L99 # !G1L37 # !G1L57);
G1_REG_Q[19] = DFFEA(G1_REG_Q[19]_lut_out, GLOBAL(K1_CLK), !H1_TMP, , , , );


--G1_REG_Q[18] is generator_accB:inst4|REG_Q[18] at LC_X9_Y1_N4
--operation mode is normal

G1_REG_Q[18]_lut_out = G1L56 & (G1L99 # !G1L37 # !G1L57);
G1_REG_Q[18] = DFFEA(G1_REG_Q[18]_lut_out, GLOBAL(K1_CLK), !H1_TMP, , , , );


--G1_REG_Q[17] is generator_accB:inst4|REG_Q[17] at LC_X10_Y1_N8
--operation mode is normal

G1_REG_Q[17]_lut_out = G1L16 & (G1L99 # !G1L37 # !G1L57);
G1_REG_Q[17] = DFFEA(G1_REG_Q[17]_lut_out, GLOBAL(K1_CLK), !H1_TMP, , , , );


--G1_REG_Q[16] is generator_accB:inst4|REG_Q[16] at LC_X9_Y1_N7
--operation mode is normal

G1_REG_Q[16]_lut_out = G1L75 & (G1L99 # !G1L37 # !G1L57);
G1_REG_Q[16] = DFFEA(G1_REG_Q[16]_lut_out, GLOBAL(K1_CLK), !H1_TMP, , , , );


--G1_REG_Q[15] is generator_accB:inst4|REG_Q[15] at LC_X8_Y3_N6
--operation mode is normal

G1_REG_Q[15]_lut_out = G1L55 & (G1L99 # !G1L57 # !G1L37);
G1_REG_Q[15] = DFFEA(G1_REG_Q[15]_lut_out, GLOBAL(K1_CLK), !H1_TMP, , , , );


--G1_REG_Q[14] is generator_accB:inst4|REG_Q[14] at LC_X9_Y3_N4
--operation mode is normal

G1_REG_Q[14]_lut_out = G1L15 & (G1L99 # !G1L57 # !G1L37);
G1_REG_Q[14] = DFFEA(G1_REG_Q[14]_lut_out, GLOBAL(K1_CLK), !H1_TMP, , , , );


--L1L71 is VOLTAGE_CONV:inst9|add~8 at LC_X18_Y4_N7
--operation mode is normal

L1L71_carry_eqn = (!L1L01 & L1L56) # (L1L01 & L1L66);
L1L71 = H1_RAMTMP2[7] $ L1L71_carry_eqn $ V1_q_b[7];

--L1_TEMP[7] is VOLTAGE_CONV:inst9|TEMP[7] at LC_X18_Y4_N7
--operation mode is normal

L1_TEMP[7] = DFFEA(L1L71, !GLOBAL(P1_CLK), !GLOBAL(S1_EN), , !L1L64, , );


--P1_CLK is FREDEVIDER2:inst13|CLK at LC_X11_Y6_N8
--operation mode is normal

P1_CLK_lut_out = !P1_CLK;
P1_CLK = DFFEA(P1_CLK_lut_out, N1_RD, VCC, , , , );


--S1L5Q is CONV_SINGLE:inst22|CURRENT_STATE~14 at LC_X16_Y4_N8
--operation mode is normal

S1L5Q_lut_out = S1L4Q & (S1L5Q & H1_RAMTMP6[0] # !S1L46) # !S1L4Q & S1L5Q & H1_RAMTMP6[0];
S1L5Q = DFFEA(S1L5Q_lut_out, GLOBAL(CLK), VCC, , , , );


--S1L1Q is CONV_SINGLE:inst22|CURRENT_STATE~10 at LC_X16_Y3_N0
--operation mode is normal

S1L1Q_lut_out = !S1L56 & (H1_RAMTMP6[0] # !S1L2Q # !S1L07);
S1L1Q = DFFEA(S1L1Q_lut_out, GLOBAL(CLK), VCC, , , , );


--S1_EN is CONV_SINGLE:inst22|EN at LC_X16_Y3_N4
--operation mode is normal

S1_EN = !S1L5Q & S1L1Q;


--L1L64 is VOLTAGE_CONV:inst9|LessThan~8 at LC_X19_Y4_N7
--operation mode is normal

L1L64_carry_eqn = (!L1L43 & L1L44) # (L1L43 & L1L54);
L1L64 = V1_q_b[7] & (L1L64_carry_eqn # !L1L71) # !V1_q_b[7] & L1L64_carry_eqn & !L1L71;


--L2L71 is VOLTAGE_CONV:inst17|add~8 at LC_X18_Y3_N7
--operation mode is normal