scanwave.map.eqn

数字示波器的FPGA实现 VHDL编写 Quartus7.1测试通过

--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered
V2_q_b[2]_PORT_A_data_in = R2_data[2];
V2_q_b[2]_PORT_A_data_in_reg = DFFE(V2_q_b[2]_PORT_A_data_in, V2_q_b[2]_clock_0, , , );
V2_q_b[2]_PORT_A_address = BUS(R2_cnt2[0], R2_cnt2[1], R2_cnt2[2], R2_cnt2[3], R2_cnt2[4], R2_cnt2[5], R2_cnt2[6], R2_cnt2[7], R2_cnt2[8], R2_cnt2[9], R2_cnt2[10]);
V2_q_b[2]_PORT_A_address_reg = DFFE(V2_q_b[2]_PORT_A_address, V2_q_b[2]_clock_0, , , );
V2_q_b[2]_PORT_B_address = BUS(M1_COUNTER[0], M1_COUNTER[1], M1_COUNTER[2], M1_COUNTER[3], M1_COUNTER[4], M1_COUNTER[5], M1_COUNTER[6], M1_COUNTER[7], M1_COUNTER[8], M1_COUNTER[9], M1_COUNTER[10]);
V2_q_b[2]_PORT_B_address_reg = DFFE(V2_q_b[2]_PORT_B_address, V2_q_b[2]_clock_1, , , );
V2_q_b[2]_PORT_A_write_enable = VCC;
V2_q_b[2]_PORT_A_write_enable_reg = DFFE(V2_q_b[2]_PORT_A_write_enable, V2_q_b[2]_clock_0, , , );
V2_q_b[2]_PORT_B_read_enable = VCC;
V2_q_b[2]_PORT_B_read_enable_reg = DFFE(V2_q_b[2]_PORT_B_read_enable, V2_q_b[2]_clock_1, , , );
V2_q_b[2]_clock_0 = CLK;
V2_q_b[2]_clock_1 = CLK;
V2_q_b[2]_PORT_B_data_out = MEMORY(V2_q_b[2]_PORT_A_data_in_reg, , V2_q_b[2]_PORT_A_address_reg, V2_q_b[2]_PORT_B_address_reg, V2_q_b[2]_PORT_A_write_enable_reg, V2_q_b[2]_PORT_B_read_enable_reg, , , V2_q_b[2]_clock_0, V2_q_b[2]_clock_1, , , , );
V2_q_b[2] = V2_q_b[2]_PORT_B_data_out[0];


--H1_RAMTMP5[2] is BUS_1:inst5|RAMTMP5[2]
--operation mode is normal

H1_RAMTMP5[2]_lut_out = A1L35 & (H1L69 # H1_RAMTMP5[2] & X1_q_a[5]) # !A1L35 & H1_RAMTMP5[2] & X1_q_a[5];
H1_RAMTMP5[2] = DFFEA(H1_RAMTMP5[2]_lut_out, !CLK, VCC, , H1L92, , );


--V1_q_b[1] is dram:inst|altsyncram:altsyncram_component|altsyncram_3771:auto_generated|q_b[1]
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 2048, Port A Width: 1, Port B Depth: 2048, Port B Width: 1
--Port A Logical Depth: 2048, Port A Logical Width: 8, Port B Logical Depth: 2048, Port B Logical Width: 8
--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered
V1_q_b[1]_PORT_A_data_in = R1_data[1];
V1_q_b[1]_PORT_A_data_in_reg = DFFE(V1_q_b[1]_PORT_A_data_in, V1_q_b[1]_clock_0, , , );
V1_q_b[1]_PORT_A_address = BUS(R1_cnt2[0], R1_cnt2[1], R1_cnt2[2], R1_cnt2[3], R1_cnt2[4], R1_cnt2[5], R1_cnt2[6], R1_cnt2[7], R1_cnt2[8], R1_cnt2[9], R1_cnt2[10]);
V1_q_b[1]_PORT_A_address_reg = DFFE(V1_q_b[1]_PORT_A_address, V1_q_b[1]_clock_0, , , );
V1_q_b[1]_PORT_B_address = BUS(M1_COUNTER[0], M1_COUNTER[1], M1_COUNTER[2], M1_COUNTER[3], M1_COUNTER[4], M1_COUNTER[5], M1_COUNTER[6], M1_COUNTER[7], M1_COUNTER[8], M1_COUNTER[9], M1_COUNTER[10]);
V1_q_b[1]_PORT_B_address_reg = DFFE(V1_q_b[1]_PORT_B_address, V1_q_b[1]_clock_1, , , );
V1_q_b[1]_PORT_A_write_enable = VCC;
V1_q_b[1]_PORT_A_write_enable_reg = DFFE(V1_q_b[1]_PORT_A_write_enable, V1_q_b[1]_clock_0, , , );
V1_q_b[1]_PORT_B_read_enable = VCC;
V1_q_b[1]_PORT_B_read_enable_reg = DFFE(V1_q_b[1]_PORT_B_read_enable, V1_q_b[1]_clock_1, , , );
V1_q_b[1]_clock_0 = CLK;
V1_q_b[1]_clock_1 = CLK;
V1_q_b[1]_PORT_B_data_out = MEMORY(V1_q_b[1]_PORT_A_data_in_reg, , V1_q_b[1]_PORT_A_address_reg, V1_q_b[1]_PORT_B_address_reg, V1_q_b[1]_PORT_A_write_enable_reg, V1_q_b[1]_PORT_B_read_enable_reg, , , V1_q_b[1]_clock_0, V1_q_b[1]_clock_1, , , , );
V1_q_b[1] = V1_q_b[1]_PORT_B_data_out[0];


--H1_RAMTMP2[1] is BUS_1:inst5|RAMTMP2[1]
--operation mode is normal

H1_RAMTMP2[1]_lut_out = A1L45 & (H1L59 # H1_RAMTMP2[1] & X1_q_a[6]) # !A1L45 & H1_RAMTMP2[1] & X1_q_a[6];
H1_RAMTMP2[1] = DFFEA(H1_RAMTMP2[1]_lut_out, !CLK, VCC, , H1L92, , );


--V2_q_b[1] is dram:inst14|altsyncram:altsyncram_component|altsyncram_3771:auto_generated|q_b[1]
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 2048, Port A Width: 1, Port B Depth: 2048, Port B Width: 1
--Port A Logical Depth: 2048, Port A Logical Width: 8, Port B Logical Depth: 2048, Port B Logical Width: 8
--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered
V2_q_b[1]_PORT_A_data_in = R2_data[1];
V2_q_b[1]_PORT_A_data_in_reg = DFFE(V2_q_b[1]_PORT_A_data_in, V2_q_b[1]_clock_0, , , );
V2_q_b[1]_PORT_A_address = BUS(R2_cnt2[0], R2_cnt2[1], R2_cnt2[2], R2_cnt2[3], R2_cnt2[4], R2_cnt2[5], R2_cnt2[6], R2_cnt2[7], R2_cnt2[8], R2_cnt2[9], R2_cnt2[10]);
V2_q_b[1]_PORT_A_address_reg = DFFE(V2_q_b[1]_PORT_A_address, V2_q_b[1]_clock_0, , , );
V2_q_b[1]_PORT_B_address = BUS(M1_COUNTER[0], M1_COUNTER[1], M1_COUNTER[2], M1_COUNTER[3], M1_COUNTER[4], M1_COUNTER[5], M1_COUNTER[6], M1_COUNTER[7], M1_COUNTER[8], M1_COUNTER[9], M1_COUNTER[10]);
V2_q_b[1]_PORT_B_address_reg = DFFE(V2_q_b[1]_PORT_B_address, V2_q_b[1]_clock_1, , , );
V2_q_b[1]_PORT_A_write_enable = VCC;
V2_q_b[1]_PORT_A_write_enable_reg = DFFE(V2_q_b[1]_PORT_A_write_enable, V2_q_b[1]_clock_0, , , );
V2_q_b[1]_PORT_B_read_enable = VCC;
V2_q_b[1]_PORT_B_read_enable_reg = DFFE(V2_q_b[1]_PORT_B_read_enable, V2_q_b[1]_clock_1, , , );
V2_q_b[1]_clock_0 = CLK;
V2_q_b[1]_clock_1 = CLK;
V2_q_b[1]_PORT_B_data_out = MEMORY(V2_q_b[1]_PORT_A_data_in_reg, , V2_q_b[1]_PORT_A_address_reg, V2_q_b[1]_PORT_B_address_reg, V2_q_b[1]_PORT_A_write_enable_reg, V2_q_b[1]_PORT_B_read_enable_reg, , , V2_q_b[1]_clock_0, V2_q_b[1]_clock_1, , , , );
V2_q_b[1] = V2_q_b[1]_PORT_B_data_out[0];


--H1_RAMTMP5[1] is BUS_1:inst5|RAMTMP5[1]
--operation mode is normal

H1_RAMTMP5[1]_lut_out = A1L45 & (H1L69 # H1_RAMTMP5[1] & X1_q_a[5]) # !A1L45 & H1_RAMTMP5[1] & X1_q_a[5];
H1_RAMTMP5[1] = DFFEA(H1_RAMTMP5[1]_lut_out, !CLK, VCC, , H1L92, , );


--V1_q_b[0] is dram:inst|altsyncram:altsyncram_component|altsyncram_3771:auto_generated|q_b[0]
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 2048, Port A Width: 1, Port B Depth: 2048, Port B Width: 1
--Port A Logical Depth: 2048, Port A Logical Width: 8, Port B Logical Depth: 2048, Port B Logical Width: 8
--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered
V1_q_b[0]_PORT_A_data_in = R1_data[0];
V1_q_b[0]_PORT_A_data_in_reg = DFFE(V1_q_b[0]_PORT_A_data_in, V1_q_b[0]_clock_0, , , );
V1_q_b[0]_PORT_A_address = BUS(R1_cnt2[0], R1_cnt2[1], R1_cnt2[2], R1_cnt2[3], R1_cnt2[4], R1_cnt2[5], R1_cnt2[6], R1_cnt2[7], R1_cnt2[8], R1_cnt2[9], R1_cnt2[10]);
V1_q_b[0]_PORT_A_address_reg = DFFE(V1_q_b[0]_PORT_A_address, V1_q_b[0]_clock_0, , , );
V1_q_b[0]_PORT_B_address = BUS(M1_COUNTER[0], M1_COUNTER[1], M1_COUNTER[2], M1_COUNTER[3], M1_COUNTER[4], M1_COUNTER[5], M1_COUNTER[6], M1_COUNTER[7], M1_COUNTER[8], M1_COUNTER[9], M1_COUNTER[10]);
V1_q_b[0]_PORT_B_address_reg = DFFE(V1_q_b[0]_PORT_B_address, V1_q_b[0]_clock_1, , , );
V1_q_b[0]_PORT_A_write_enable = VCC;
V1_q_b[0]_PORT_A_write_enable_reg = DFFE(V1_q_b[0]_PORT_A_write_enable, V1_q_b[0]_clock_0, , , );
V1_q_b[0]_PORT_B_read_enable = VCC;
V1_q_b[0]_PORT_B_read_enable_reg = DFFE(V1_q_b[0]_PORT_B_read_enable, V1_q_b[0]_clock_1, , , );
V1_q_b[0]_clock_0 = CLK;
V1_q_b[0]_clock_1 = CLK;
V1_q_b[0]_PORT_B_data_out = MEMORY(V1_q_b[0]_PORT_A_data_in_reg, , V1_q_b[0]_PORT_A_address_reg, V1_q_b[0]_PORT_B_address_reg, V1_q_b[0]_PORT_A_write_enable_reg, V1_q_b[0]_PORT_B_read_enable_reg, , , V1_q_b[0]_clock_0, V1_q_b[0]_clock_1, , , , );
V1_q_b[0] = V1_q_b[0]_PORT_B_data_out[0];


--H1_RAMTMP2[0] is BUS_1:inst5|RAMTMP2[0]
--operation mode is normal

H1_RAMTMP2[0]_lut_out = A1L55 & (H1L59 # H1_RAMTMP2[0] & X1_q_a[6]) # !A1L55 & H1_RAMTMP2[0] & X1_q_a[6];
H1_RAMTMP2[0] = DFFEA(H1_RAMTMP2[0]_lut_out, !CLK, VCC, , H1L92, , );


--V2_q_b[0] is dram:inst14|altsyncram:altsyncram_component|altsyncram_3771:auto_generated|q_b[0]
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 2048, Port A Width: 1, Port B Depth: 2048, Port B Width: 1
--Port A Logical Depth: 2048, Port A Logical Width: 8, Port B Logical Depth: 2048, Port B Logical Width: 8
--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered
V2_q_b[0]_PORT_A_data_in = R2_data[0];
V2_q_b[0]_PORT_A_data_in_reg = DFFE(V2_q_b[0]_PORT_A_data_in, V2_q_b[0]_clock_0, , , );
V2_q_b[0]_PORT_A_address = BUS(R2_cnt2[0], R2_cnt2[1], R2_cnt2[2], R2_cnt2[3], R2_cnt2[4], R2_cnt2[5], R2_cnt2[6], R2_cnt2[7], R2_cnt2[8], R2_cnt2[9], R2_cnt2[10]);
V2_q_b[0]_PORT_A_address_reg = DFFE(V2_q_b[0]_PORT_A_address, V2_q_b[0]_clock_0, , , );
V2_q_b[0]_PORT_B_address = BUS(M1_COUNTER[0], M1_COUNTER[1], M1_COUNTER[2], M1_COUNTER[3], M1_COUNTER[4], M1_COUNTER[5], M1_COUNTER[6], M1_COUNTER[7], M1_COUNTER[8], M1_COUNTER[9], M1_COUNTER[10]);
V2_q_b[0]_PORT_B_address_reg = DFFE(V2_q_b[0]_PORT_B_address, V2_q_b[0]_clock_1, , , );
V2_q_b[0]_PORT_A_write_enable = VCC;
V2_q_b[0]_PORT_A_write_enable_reg = DFFE(V2_q_b[0]_PORT_A_write_enable, V2_q_b[0]_clock_0, , , );
V2_q_b[0]_PORT_B_read_enable = VCC;
V2_q_b[0]_PORT_B_read_enable_reg = DFFE(V2_q_b[0]_PORT_B_read_enable, V2_q_b[0]_clock_1, , , );
V2_q_b[0]_clock_0 = CLK;
V2_q_b[0]_clock_1 = CLK;
V2_q_b[0]_PORT_B_data_out = MEMORY(V2_q_b[0]_PORT_A_data_in_reg, , V2_q_b[0]_PORT_A_address_reg, V2_q_b[0]_PORT_B_address_reg, V2_q_b[0]_PORT_A_write_enable_reg, V2_q_b[0]_PORT_B_read_enable_reg, , , V2_q_b[0]_clock_0, V2_q_b[0]_clock_1, , , , );
V2_q_b[0] = V2_q_b[0]_PORT_B_data_out[0];


--H1_RAMTMP5[0] is BUS_1:inst5|RAMTMP5[0]
--operation mode is normal

H1_RAMTMP5[0]_lut_out = A1L55 & (H1L69 # H1_RAMTMP5[0] & X1_q_a[5]) # !A1L55 & H1_RAMTMP5[0] & X1_q_a[5];
H1_RAMTMP5[0] = DFFEA(H1_RAMTMP5[0]_lut_out, !CLK, VCC, , H1L92, , );


--H1_P0_OUT[7] is BUS_1:inst5|P0_OUT[7]
--operation mode is normal

H1_P0_OUT[7]_lut_out = J1_TEMP[15] & (H1L02 # !H1L29) # !J1_TEMP[15] & H1L02 & H1L29;
H1_P0_OUT[7]_sload_eqn = (H1L19 & J1_TEMP[7]) # (!H1L19 & H1_P0_OUT[7]_lut_out);
H1_P0_OUT[7] = DFFEA(H1_P0_OUT[7]_sload_eqn, CLK, VCC, , H1L82, , );


--H1_GX is BUS_1:inst5|GX
--operation mode is normal

H1_GX_lut_out = H1L82 & (H1L19 # !H1L29 # !H1L39);
H1_GX = DFFEA(H1_GX_lut_out, CLK, VCC, , , , );


--H1_P0_OUT[6] is BUS_1:inst5|P0_OUT[6]
--operation mode is normal

H1_P0_OUT[6]_lut_out = J1_TEMP[14] & (H1L12 # !H1L29) # !J1_TEMP[14] & H1L12 & H1L29;
H1_P0_OUT[6]_sload_eqn = (H1L19 & J1_TEMP[6]) # (!H1L19 & H1_P0_OUT[6]_lut_out);
H1_P0_OUT[6] = DFFEA(H1_P0_OUT[6]_sload_eqn, CLK, VCC, , H1L82, , );


--H1_P0_OUT[5] is BUS_1:inst5|P0_OUT[5]
--operation mode is normal

H1_P0_OUT[5]_lut_out = J1_TEMP[13] & (H1L22 # !H1L29) # !J1_TEMP[13] & H1L22 & H1L29;
H1_P0_OUT[5]_sload_eqn = (H1L19 & J1_TEMP[5]) # (!H1L19 & H1_P0_OUT[5]_lut_out);
H1_P0_OUT[5] = DFFEA(H1_P0_OUT[5]_sload_eqn, CLK, VCC, , H1L82, , );


--H1_P0_OUT[4] is BUS_1:inst5|P0_OUT[4]
--operation mode is normal

H1_P0_OUT[4]_lut_out = J1_TEMP[12] & (H1L32 # !H1L29) # !J1_TEMP[12] & H1L32 & H1L29;
H1_P0_OUT[4]_sload_eqn = (H1L19 & J1_TEMP[4]) # (!H1L19 & H1_P0_OUT[4]_lut_out);
H1_P0_OUT[4] = DFFEA(H1_P0_OUT[4]_sload_eqn, CLK, VCC, , H1L82, , );


--H1_P0_OUT[3] is BUS_1:inst5|P0_OUT[3]
--operation mode is normal

H1_P0_OUT[3]_lut_out = J1_TEMP[11] & (H1L42 # !H1L29) # !J1_TEMP[11] & H1L42 & H1L29;
H1_P0_OUT[3]_sload_eqn = (H1L19 & J1_TEMP[3]) # (!H1L19 & H1_P0_OUT[3]_lut_out);
H1_P0_OUT[3] = DFFEA(H1_P0_OUT[3]_sload_eqn, CLK, VCC, , H1L82, , );


--H1_P0_OUT[2] is BUS_1:inst5|P0_OUT[2]
--operation mode is normal

H1_P0_OUT[2]_lut_out = J1_TEMP[10] & (H1L52 # !H1L29) # !J1_TEMP[10] & H1L52 & H1L29;
H1_P0_OUT[2]_sload_eqn = (H1L19 & J1_TEMP[2]) # (!H1L19 & H1_P0_OUT[2]_lut_out);
H1_P0_OUT[2] = DFFEA(H1_P0_OUT[2]_sload_eqn, CLK, VCC, , H1L82, , );


--H1_P0_OUT[1] is BUS_1:inst5|P0_OUT[1]
--operation mode is normal

H1_P0_OUT[1]_lut_out = J1_TEMP[9] & (H1L62 # !H1L29) # !J1_TEMP[9] & H1L62 & H1L29;
H1_P0_OUT[1]_sload_eqn = (H1L19 & J1_TEMP[1]) # (!H1L19 & H1_P0_OUT[1]_lut_out);
H1_P0_OUT[1] = DFFEA(H1_P0_OUT[1]_sload_eqn, CLK, VCC, , H1L82, , );


--H1_P0_OUT[0] is BUS_1:inst5|P0_OUT[0]
--operation mode is normal

H1_P0_OUT[0]_lut_out = J1_TEMP[8] & (H1L72 # !H1L29) # !J1_TEMP[8] & H1L72 & H1L29;
H1_P0_OUT[0]_sload_eqn = (H1L19 & J1_TEMP[0]) # (!H1L19 & H1_P0_OUT[0]_lut_out);
H1_P0_OUT[0] = DFFEA(H1_P0_OUT[0]_sload_eqn, CLK, VCC, , H1L82, , );


--H1_RAMTMP9[7] is BUS_1:inst5|RAMTMP9[7]
--operation mode is normal

H1_RAMTMP9[7]_lut_out = A1L84 & (H1L89 # H1_RAMTMP9[7] & X1_q_a[4]) # !A1L84 & H1_RAMTMP9[7] & X1_q_a[4];
H1_RAMTMP9[7] = DFFEA(H1_RAMTMP9[7]_lut_out, !CLK, VCC, , H1L92, , );


--H1_RAMTMP9[6] is BUS_1:inst5|RAMTMP9[6]
--operation mode is normal

H1_RAMTMP9[6]_lut_out = A1L94 & (H1L89 # H1_RAMTMP9[6] & X1_q_a[4]) # !A1L94 & H1_RAMTMP9[6] & X1_q_a[4];
H1_RAMTMP9[6] = DFFEA(H1_RAMTMP9[6]_lut_out, !CLK, VCC, , H1L92, , );


--G1L72 is generator_accB:inst4|add~14
--operation mode is arithmetic

G1L72_carry_eqn = G1L62;
G1L72 = G1_REG_Q[13] $ H1_RAMTMP9[5] $ G1L72_carry_eqn;

--G1L82 is generator_accB:inst4|add~14COUT
--operation mode is arithmetic

G1L82 = CARRY(G1_REG_Q[13] & !H1_RAMTMP9[5] & !G1L62 # !G1_REG_Q[13] & (!G1L62 # !H1_RAMTMP9[5]));


--R1_data[7] is AD_SRAM:inst19|data[7]
--operation mode is normal

R1_data[7]_lut_out = N1_ADOUT_A[7];
R1_data[7] = DFFEA(R1_data[7]_lut_out, CLK, VCC, , R1L05, , );


--R1_cnt2[0] is AD_SRAM:inst19|cnt2[0]
--operation mode is normal

R1_cnt2[0]_lut_out = R1L1 & (R1L65 # R1L75 # R1L85);
R1_cnt2[0] = DFFEA(R1_cnt2[0]_lut_out, CLK, !S1_EN, , R1L15, , );


--R1_cnt2[1] is AD_SRAM:inst19|cnt2[1]
--operation mode is normal

R1_cnt2[1]_lut_out = R1L3;
R1_cnt2[1] = DFFEA(R1_cnt2[1]_lut_out, CLK, !S1_EN, , R1L15, , );


--R1_cnt2[2] is AD_SRAM:inst19|cnt2[2]
--operation mode is normal

R1_cnt2[2]_lut_out = R1L5;
R1_cnt2[2] = DFFEA(R1_cnt2[2]_lut_out, CLK, !S1_EN, , R1L15, , );


--R1_cnt2[3] is AD_SRAM:inst19|cnt2[3]
--operation mode is normal

R1_cnt2[3]_lut_out = R1L7;
R1_cnt2[3] = DFFEA(R1_cnt2[3]_lut_out, CLK, !S1_EN, , R1L15, , );


--R1_cnt2[4] is AD_SRAM:inst19|cnt2[4]
--operation mode is normal

R1_cnt2[4]_lut_out = R1L9;
R1_cnt2[4] = DFFEA(R1_cnt2[4]_lut_out, CLK, !S1_EN, , R1L15, , );


--R1_cnt2[5] is AD_SRAM:inst19|cnt2[5]
--operation mode is normal

R1_cnt2[5]_lut_out = R1L11;
R1_cnt2[5] = DFFEA(R1_cnt2[5]_lut_out, CLK, !S1_EN, , R1L15, , );


--R1_cnt2[6] is AD_SRAM:inst19|cnt2[6]
--operation mode is normal

R1_cnt2[6]_lut_out = R1L31;
R1_cnt2[6] = DFFEA(R1_cnt2[6]_lut_out, CLK, !S1_EN, , R1L15, , );


--R1_cnt2[7] is AD_SRAM:inst19|cnt2[7]
--operation mode is normal

R1_cnt2[7]_lut_out = R1L51;
R1_cnt2[7] = DFFEA(R1_cnt2[7]_lut_out, CLK, !S1_EN, , R1L15, , );


--R1_cnt2[8] is AD_SRAM:inst19|cnt2[8]
--operation mode is normal

R1_cnt2[8]_lut_out = R1L71;
R1_cnt2[8] = DFFEA(R1_cnt2[8]_lut_out, CLK, !S1_EN, , R1L15, , );


--R1_cnt2[9] is AD_SRAM:inst19|cnt2[9]
--operation mode is normal

R1_cnt2[9]_lut_out = R1L91;
R1_cnt2[9] = DFFEA(R1_cnt2[9]_lut_out, CLK, !S1_EN, , R1L15, , );


--R1_cnt2[10] is AD_SRAM:inst19|cnt2[10]
--operation mode is normal

R1_cnt2[10]_lut_out = R1L12;
R1_cnt2[10] = DFFEA(R1_cnt2[10]_lut_out, CLK, !S1_EN, , R1L15, , );


--M1_COUNTER[0] is GET_RDADDR:inst10|COUNTER[0]
--operation mode is normal

M1_COUNTER[0]_lut_out = M1L1;
M1_COUNTER[0] = DFFEA(M1_COUNTER[0]_lut_out, !P1_CLK, !G1_START, , M1L44, , );


--M1_COUNTER[1] is GET_RDADDR:inst10|COUNTER[1]
--operation mode is normal

M1_COUNTER[1]_lut_out = M1L3;
M1_COUNTER[1] = DFFEA(M1_COUNTER[1]_lut_out, !P1_CLK, !G1_START, , M1L44, , );


--M1_COUNTER[2] is